Parallel AI Chip Compute Node Load Distribution

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Solution Overview

Problem

There is a need for an artificial intelligence chip that can efficiently compute artificial neural network algorithms on-device, particularly in edge devices, to address issues of network traffic, energy efficiency, and privacy protection.

Innovation Solution

A compute node with a communication interface, memory, and processor that can symmetrically expand to multiple nodes, allowing for parallel processing of computational models by distributing computational loads and selecting a master node based on contributable loads, and an AI accelerator for generating and distributing intermediate data.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If computational models are processed on a single device, then privacy protection is improved, but computing speed and response time deteriorate

Engineering Contradiction:
Improveprivacy protectionVSAvoidcomputing speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system segments the computational model processing into multiple compute nodes, where each node processes a portion of the computational load. The home node receives input data and coordinates with other compute nodes to distribute processing tasks, enabling parallel computation while keeping data processing distributed across multiple devices for enhanced privacy protection

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from single-device processing to multi-node distributed processing by adding the dimension of spatial distribution. Multiple compute nodes are connected through communication interfaces, creating a distributed computing architecture that processes computational models across multiple devices simultaneously, improving both speed and privacy

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If multiple compute nodes are used for parallel processing, then computing speed is improved, but system complexity increases

Engineering Contradiction:
Improvecomputing speedVSAvoidsystem complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent merges multiple compute nodes into a coordinated system where nodes communicate through standardized interfaces. The home node consolidates the coordination function, receiving input data and managing the distribution of computational tasks to other nodes, while maintaining a unified processing workflow that simplifies the overall system architecture

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

Each compute node is designed with universal functionality, capable of performing various computational tasks and communicating through standardized interfaces. The home node can serve multiple functions including receiving input data, coordinating processing, and aggregating results, while other nodes can dynamically assume different roles based on their computational capabilities and current load

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Measurement precision

If computational load is distributed among multiple nodes, then accuracy is improved, but communication overhead increases

Engineering Contradiction:
ImproveaccuracyVSAvoidcommunication overhead
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The system maintains continuous useful action by having the home node continuously receive input data and coordinate with compute nodes that are continuously processing computational models. The parallel processing architecture ensures that computation continues without interruption across multiple nodes, improving accuracy through ensemble methods while minimizing communication gaps

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS11615287B2Processing computational models in parallel
Publication Date: 2023.03.28 LG ELECTRONICS INC
  • US11615287B2 patent drawing
  • US11615287B2 patent drawing
  • US11615287B2 patent drawing

AI summary

The present disclosure relates to an artificial intelligence chip for processing computations for machine learning models that provides a compute node and a method of processing a computational model using a plurality of compute nodes in parallel. In some embodiments, the compute node, comprises: a communication interface configured to communicate with one or more other compute nodes; a memory configured to store shared data that is shared with the one or more other compute nodes; and a processor configured to: determine an expected computational load for processing a computational model for input data; obtain a contributable computational load of the compute node and the one or more other compute nodes; and select a master node to distribute the determined expected computational load based on the obtained contributable computational load. Consequently, learning and inference can be performed efficiently on-device.