Electronic Device Parallel Application Compilation Booting

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Solution Overview

Problem

Existing electronic devices face inefficiencies in the booting process due to the sequential compilation of application programs during startup, which can significantly prolong the time required for system initialization.

Innovation Solution

Implementing a method for parallel compilation of multiple application programs using multiple cores during the booting operation, with a rebooting mechanism for applications that fail compilation, allowing for series compilation using a single core during the rebooting process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If sequential compilation of application programs is performed during booting operation, then compilation reliability is improved, but booting time is significantly prolonged

Engineering Contradiction:
Improvecompilation reliabilityVSAvoidbooting time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent segments the compilation process into two distinct modes: parallel compilation for normally operating applications and series compilation for applications requiring rebooting. This segmentation allows the system to handle different compilation scenarios differently, achieving both speed and reliability

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic switching between parallel and series compilation modes based on system state (booting operation vs. rebooting operation). This dynamic approach allows the system to optimize compilation strategy according to operational context, resolving the contradiction between speed and reliability

Inventive Principle:
Principle #15Dynamics

2Loss of time

If parallel compilation of multiple application programs is performed using multiple cores during booting, then booting time is reduced, but system stability may be compromised due to compilation failures

Engineering Contradiction:
Improvebooting timeVSAvoidsystem stability
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

The patent prepares for potential compilation failures by having a series compilation mode ready as a backup. When parallel compilation fails, the system automatically switches to series compilation during rebooting, cushioning against the negative effects of compilation failures while maintaining overall system stability

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Solution Approach 2:

The patent implements feedback mechanisms to monitor compilation results. Based on whether parallel compilation succeeds or fails, the system adjusts its behavior by either completing the booting process or initiating a rebooting operation with series compilation, ensuring system stability

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS11435985B2Electronic device and operation method thereof
Publication Date: 2022.09.06 SAMSUNG ELECTRONICS CO LTD
  • US11435985B2 patent drawing
  • US11435985B2 patent drawing
  • US11435985B2 patent drawing

AI summary

The electronic device may comprise: a display; a processor electrically connected to the display and including a plurality of cores; and a memory electrically connected to the processor, wherein the memory is configured to store a plurality of application programs, and stores instructions which, when executed, allow the processor to perform parallel compilation of two or more application programs among the plurality of application programs by using two or more cores among the plurality of cores during a booting operation, and when at least one application program which has failed to be compiled is sensed, perform a rebooting operation, and perform series compilation of the at least one application program which has failed to be compiled, by using one core among the plurality of cores during the rebooting operation. Other embodiments may also be possible.