Parallel Arbiter for Multi-Port Memory Arbitration

The patent segments the arbitration process into multiple independent parallel operations. Instead of sequentially arbitrating between ports and then between memory banks, the system divides the arbitration into independent stages: port-to-interface arbitration and interface-to-memory bank arbitration can occur simultaneously. This segmentation allows multiple arbitration decisions to be made in parallel, dramatically increasing arbitration speed and reducing packet writing delays.

The patent introduces a new dimension of parallelism by adding intermediate interfaces between ports and memory banks. This creates a two-dimensional arbitration space where port interfaces can be arbitrated independently from memory bank interfaces. The intermediate interface layer enables simultaneous arbitration operations that were not possible in traditional single-dimension sequential arbitration schemes.

The arbitration functionality is segmented into distributed arbitration units rather than centralized in a single complex arbiter device. Each interface or memory bank can have its own simplified arbitration logic, allowing independent decision-making. This segmentation reduces the complexity burden on any single arbiter device while maintaining the ability to manage multiple memory banks simultaneously for high productivity.

Intermediate interfaces are introduced as mediators between ports and memory banks. These interfaces handle arbitration locally, reducing the burden on the main arbiter device. The intermediary interfaces can make quick local arbitration decisions and only communicate with the main arbiter when needed, thereby reducing overall system complexity while maintaining high memory write capacity.

The patent creates a multi-dimensional mapping structure between ports and memory interfaces through intermediate interface layers. This allows many-to-many relationships where multiple memory interfaces can be efficiently distributed across fewer ports. The intermediate interfaces provide an additional dimension for load balancing and selection distribution, making it easier to manage situations where memory interfaces exceed ports.

The arbitration system implements self-service through automated selection distribution algorithms. When memory interfaces exceed ports, the system automatically balances the load across available interfaces without manual intervention. The arbitration logic dynamically assigns memory interfaces to ports based on current availability and usage, ensuring efficient distribution while maintaining high adaptability.