Parallel Arithmetic Circuits for Combinatorial Optimization

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Solution Overview

Problem

Combinatorial optimization problems, common in fields like finance and logistics, face challenges due to the 'combinatorial explosion' issue, where the number of combinations increases exponentially, making it difficult to calculate optimal or approximate solutions within a practical time.

Innovation Solution

An information processing system comprising multiple arithmetic circuits and a data exchange circuit that update vectors based on corresponding variables, weight, and add problem terms, with different coefficients set in each circuit, and a data exchange circuit for exchanging vectors or coefficients between circuits, facilitating parallel processing and distributed calculations to solve combinatorial optimization problems.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional sequential processing is used to solve combinatorial optimization problems, then calculation accuracy can be maintained, but the calculation time becomes excessively long due to combinatorial explosion

Engineering Contradiction:
Improvesolution accuracyVSAvoidcalculation time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent divides the combinatorial optimization problem into multiple sub-problems that can be processed in parallel. The arithmetic circuits are segmented to handle different portions of the calculation simultaneously, reducing the overall computation time while maintaining solution accuracy through coordinated processing of discrete variables.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from sequential one-dimensional processing to multi-dimensional parallel processing by deploying multiple arithmetic circuits that operate simultaneously. This dimensional expansion allows the system to explore the solution space more efficiently by evaluating multiple combinations in parallel rather than sequentially.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If the number of arithmetic circuits is increased to improve processing speed, then parallel processing capability increases, but device complexity and cost increase

Engineering Contradiction:
Improveprocessing speedVSAvoidsystem complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent designs arithmetic circuits with universal functionality that can handle multiple operations required for combinatorial optimization. Each circuit is configured to process different aspects of the same problem type, allowing for scalable parallel processing without proportionally increasing overall system complexity. The circuits share common operational frameworks and data structures.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent implements a hierarchical structure where arithmetic circuits are organized in nested configurations. Simpler circuit units are nested within more complex processing layers, allowing the system to achieve high processing speed through parallel operation of multiple levels while managing complexity through structured organization and modular design.

Inventive Principle:
Principle #7Nested doll (Nesting)

Data Source

PatentUS20220012017A1Information processing device, information processing system, information processing method, and storage medium
Publication Date: 2022.01.13 KK TOSHIBA
  • US20220012017A1 patent drawing
  • US20220012017A1 patent drawing
  • US20220012017A1 patent drawing

AI summary

An information processing device includes arithmetic circuits each configured to repeatedly update a first vector which has a first variable as an element and a second vector which has a second variable corresponding to the first variable as an element, and a data exchange circuit. Each arithmetic circuit is configured to update the first variable based on the corresponding second variable, weight the first variable with a first coefficient and add the weighted first variable to the corresponding second variable, calculate a problem term using a plurality of the first variables, and add the problem term to the second variable; different values are set as the first coefficients in the respective arithmetic circuits. The data exchange circuit is configured to execute at least one of exchange of the first vector and the second vector or exchange of the first coefficients between the arithmetic circuits.