Parallel Arithmetic Device Instruction Memory Context Management
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Solution Overview
Problem
Related-art dynamically reconfigurable processors face inefficiencies in using circuit resources due to the need to issue numerous instructions for both processor elements and switch elements, especially when processing multiple sets of data in parallel, leading to suboptimal performance and resource utilization.
Innovation Solution
A parallel arithmetic device with a status management section, processor elements, and switch elements that include instruction memories, allowing for the storage and execution of operation instructions across multiple contexts, enabling efficient parallel arithmetic processing by dynamically configuring the circuit with a smaller number of instructions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a related-art dynamically reconfigurable processor issues operation instructions to each processor element and switch element for parallel processing, then parallel processing capability is achieved, but the number of instructions stored in memory increases enormously
Solution Approach 1:
The patent merges the control of multiple processor elements into a single instruction stream. Instead of issuing separate instructions to each processor element and switch element, a single operation instruction is broadcast to all processor elements simultaneously, enabling parallel processing without proportionally increasing the instruction storage requirement.
Solution Approach 2:
The processor elements are designed with universal functionality where each element can perform the same operation simultaneously on different data. This allows a single instruction to control multiple identical processing units, reducing the need for duplicate instructions for each element while maintaining parallel processing capability.
2Ease of operation
If a related-art dynamically reconfigurable processor stores numerous instructions for each processor element and switch element, then complete control over parallel processing is achieved, but circuit resource efficiency decreases
Solution Approach 1:
The patent combines the control functions for multiple processor elements into a unified instruction issuance mechanism. A single instruction from one control unit simultaneously controls multiple processor elements and their interconnections, maintaining precise control while simplifying the overall control structure and improving circuit resource efficiency.
Solution Approach 2:
The patent segments the processing function across multiple identical processor elements that can be independently activated by a single instruction. This segmentation allows parallel execution without requiring separate control paths, reducing the complexity of instruction storage and management while maintaining complete control over each processing element.
Data Source
AI summary
A parallel arithmetic device includes a status management section, a plurality of processor elements, and a plurality of switch elements for determining the relation of coupling of each of the processor elements. Each of the processor elements includes an instruction memory for memorizing a plurality of operation instructions corresponding respectively to a plurality of contexts so that an operation instruction corresponding to the context selected by the status management section is read out, and a plurality of arithmetic units for performing arithmetic processes in parallel on a plurality of sets of input data in a manner compliant with the operation instruction read out from the instruction memory.