Parallel Computer Average Calculation Circuitry Overflow Prevention
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Solution Overview
Problem
Traditional parallel computer systems face issues with overflow during reduction calculations, leading to incorrect results due to higher bits being lost, and require bit expansion to prevent overflow, which increases data transmission and bandwidth usage.
Innovation Solution
An information processing apparatus in a parallel computer system performs average calculations by waiting for data from other nodes, calculating the average value, and transmitting it to another node, using a circuitry configuration that avoids bit expansion by shifting and omitting lower bits, thus preventing overflow without increasing the bit number.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If bit expansion is performed each time a calculation is performed to prevent overflow, then calculation accuracy is improved, but data transmission volume increases and bandwidth is wasted
Solution Approach 1:
The patent performs preliminary bit expansion only when necessary (when overflow is detected or anticipated) rather than expanding bits unconditionally before every calculation. The system monitors calculation results and dynamically decides whether bit expansion is needed, thus preventing unnecessary data transmission while maintaining calculation accuracy when required
Solution Approach 2:
The patent dynamically changes the bit width parameter based on calculation needs. Instead of maintaining a fixed expanded bit width, the system adjusts the bit width to match the actual requirements of each calculation, reducing data transmission volume while preserving necessary precision
2Reliability
If bit expansion is performed to prevent overflow during reduction calculations, then calculation reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies bit expansion partially rather than universally. Instead of expanding bits for all calculations, the system performs bit expansion only for specific operations where overflow risk is identified, thereby maintaining calculation reliability for critical operations while avoiding the complexity overhead of universal bit expansion infrastructure
3Device complexity
If traditional reduction calculation is performed with fixed bit width, then device complexity is reduced, but calculation precision deteriorates due to overflow
Solution Approach 1:
The patent introduces dynamic bit width adjustment to the previously static fixed-bit system. The bit width becomes a dynamic parameter that adapts based on calculation requirements, allowing the system to maintain low complexity for simple operations while automatically increasing precision when overflow conditions are detected or anticipated
Data Source
AI summary
In a parallel computer system having multiple information processing apparatuses, a first information processing apparatus includes circuitry configured to wait for calculation target data from each of one or more other information processing apparatuses being included in the plurality of information processing apparatus; carry out an average calculation that calculates an average value of a plurality of calculation target data including the waited calculation target data; and transmit the calculated average value to a second information processing apparatus being one of the plurality of information processing apparatuses and being different from the other information processing apparatuses. This configuration makes it possible to achieve highly-precise collective average calculation without requiring bit expansion.