Parallel Bank Testing in Memory Devices
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Solution Overview
Problem
The increasing complexity and capacitance of semiconductor memory devices lead to overhead in performing self-tests and analyzing results, making it challenging to efficiently detect defective memory banks during the manufacturing process and operation.
Innovation Solution
A memory device with a built-in self-test (BIST) circuit that selects target banks in various combinations for parallel testing, using a comparator to output fail signals and an analysis circuit to update fail information and determine defective banks, thereby reducing the overhead of analyzing test results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional self-test methods are used on high-capacitance memory devices, then test coverage is achieved, but overhead for analyzing test results increases significantly
Solution Approach 1:
The memory device is divided into multiple memory banks, and the self-test function is segmented to operate independently on each bank. The BIST circuit selectively activates specific memory banks for testing while others remain operational, dividing the testing task into manageable segments that reduce overall analysis overhead.
Solution Approach 2:
The BIST circuit performs preliminary self-testing operations on memory banks before they are needed for normal operation. By proactively testing memory banks and identifying defects early, the system avoids the overhead of analyzing test results during critical operation phases, as the testing is already completed in advance.
2Reliability
If all memory banks are tested sequentially, then thorough defect detection is achieved, but testing time and system performance degrade
Solution Approach 1:
The memory system is segmented into multiple independent banks that can be tested simultaneously. The BIST circuit can activate multiple memory banks in parallel for self-testing, allowing thorough defect detection across all banks without requiring sequential testing, thus maintaining high productivity while ensuring reliable defect detection.
Solution Approach 2:
While some memory banks are undergoing self-testing, other banks remain active and continue to serve data requests. This continuous operation ensures that the memory system maintains useful action throughout the testing process, avoiding performance degradation that would occur if all banks were taken offline for sequential testing.
3Loss of information
If the analysis circuit processes test results from all memory banks, then complete fail information is obtained, but the burden on the analysis circuit increases
Solution Approach 1:
The BIST circuit extracts and processes fail information locally within each memory bank's self-test operation. By handling analysis at the bank level rather than consolidating all results to a central analysis circuit, the burden on the analysis circuit is significantly reduced while still obtaining complete fail information across all banks through distributed processing.
Data Source
AI summary
A memory device includes: a built-in self-test circuit configured to select a first target bank and a second target bank for each of a plurality of row addresses such that each of a plurality of memory banks is selected as the first target bank and the second target bank at least once, and to perform parallel tests on the first and second target banks for each of the plurality of row addresses; a comparator configured to compare first data output from the first target bank and second data output from the second target bank, and to output a fail signal according to a comparison result thereof; and a built-in analysis circuit configured to update a fail bank table indicating fail information of each of the plurality of memory banks, in response to the fail signal, and to determine a defective bank by referring to the fail bank table.