Parallel BCH ECC Circuit for Low-Latency Memory Read Correction
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Solution Overview
Problem
As memory cells become smaller and denser, they become more prone to errors due to factors like storage charge loss and cosmic rays, leading to increased error probability in nonvolatile memory technologies such as NAND Flash and Phase Change Memories, especially in multi-level architectures where read margins decrease.
Innovation Solution
Implementing a high-speed error correction code (ECC) process based on parallel encoding and decoding techniques using a 2-bit error correcting binary Bose-Chaudhuri-Hocquenghem (BCH) code, which supplements user data with parity bits and employs a BCH decoder that avoids division operations in a Galois Field, optimizing latency and area occupancy in memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are made smaller and denser, then storage capacity increases, but error probability increases
Solution Approach 1:
The error correction function is segmented into specialized hardware circuits (syndrome generator, error locator, error corrector) that operate independently and in parallel with the memory array, allowing error correction to be performed on specific error-prone bits without processing the entire memory block
Solution Approach 2:
An intermediary error correction system is introduced between the memory cells and the processor. This system includes syndrome generators that detect errors, error locators that identify problematic bits, and error correctors that fix them, acting as a buffer that protects the processor from memory errors while allowing continued use of dense memory cells
2Reliability
If traditional ECC methods are used, then error correction capability is provided, but latency increases
Solution Approach 1:
Parity bits are pre-calculated and stored alongside the data bits during memory write operations. When data is read, the syndrome is immediately generated from these pre-positioned parity bits, allowing error detection and correction to begin without waiting for additional processing steps
Solution Approach 2:
The error correction process is divided into independent parallel segments: syndrome generation, error location identification, and error correction. These segments operate simultaneously on different parts of the data, reducing the total time required compared to sequential processing methods
3Reliability
If complex ECC circuits are implemented, then error correction performance improves, but area occupancy increases
Solution Approach 1:
The error correction functionality is segmented into compact modular circuits distributed throughout the memory array. Each segment handles a specific function (syndrome generation, error location, correction) and operates on localized data portions, reducing the need for large centralized correction circuits
Solution Approach 2:
Multiple error correction functions are merged into unified circuit blocks. The syndrome generator, error locator, and error corrector are combined into an integrated error correction system that shares common resources and operates cooperatively, reducing total circuit area compared to separate independent circuits for each function
Data Source
AI summary
Subject matter, for example, disclosed herein relates to an embodiment of a process, system, device, or article involving error correction codes. In a particular embodiment, an error-correcting device may comprise an input port to receive an error correcting code (ECC) based, at least in part, on contents of a memory array; a nonlinear computing block to process the ECC to provide a plurality of signals representing a nonlinear portion of an error locator polynomial; and a linear computing block to process the ECC concurrently with processing the ECC to provide a plurality of signals representing the nonlinear portion of the error locator polynomial, to provide a plurality of signals representing a linear portion of the error locator polynomial.