Parallel BCH Error Location for Faster Memory ECC Search
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Solution Overview
Problem
Conventional error location methods in non-volatile memory systems require an inordinate number of clock cycles to determine error locations, which can be time-consuming and inefficient, especially when dealing with large data sizes, and often necessitate high clock frequencies or increased logic complexity.
Innovation Solution
The implementation of parallel search operations to reduce the number of clock cycles required for determining the roots of the error locator polynomial of Bose-Chaudhuri-Hocquenghem (BCH) codes by partitioning field elements and utilizing multiple parallel search elements to compute sums based on error locator polynomial coefficients, allowing for simultaneous processing of multiple field elements and reducing the runtime.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional sequential search methods are used to determine error locations, then the error location determination is performed using simple logic, but the number of clock cycles required becomes inordinate and time-consuming
Solution Approach 1:
The patent divides the field elements into multiple partitions and processes each partition in parallel. Specifically, the 8192 field elements are segmented into groups that can be processed simultaneously by multiple search elements, reducing the sequential processing time from 8192 clock cycles to a much smaller number of parallel clock cycles.
Solution Approach 2:
The patent transitions from a one-dimensional sequential search approach to a multi-dimensional parallel processing approach by introducing multiple search elements operating simultaneously on different partitions of field elements, effectively adding a parallelism dimension to the error location determination process.
2Speed
If the clock frequency is increased to reduce error location determination time, then the processing speed increases, but the system requires very high clock frequencies that may not be easily available
Solution Approach 1:
By segmenting the search space into multiple partitions that can be processed in parallel, the patent achieves faster error location determination without requiring proportionally higher clock frequencies. The parallel structure allows the system to maintain standard clock frequencies while reducing overall processing time.
3Productivity
If parallel search operations are implemented to reduce clock cycles, then the processing speed increases, but the logic complexity and hardware requirements increase
Solution Approach 1:
The patent segments the search functionality into multiple independent search elements, each handling a specific partition of field elements. This segmentation allows for modular implementation where each search element is relatively simple, but their parallel combination achieves high overall efficiency without excessive complexity in any single component.
4Device complexity
If sequential search examines each bit location one at a time, then the logic requirements remain manageable, but the number of clock cycles required reaches 8192 for a 512 byte block
Solution Approach 1:
The patent segments the 8192 field elements into multiple partitions that can be processed simultaneously. Each partition is handled by dedicated search elements, allowing the system to examine multiple bit locations in parallel rather than sequentially, thereby reducing clock cycles from 8192 to a much smaller number while maintaining manageable logic requirements through modular design.
Solution Approach 2:
The patent adds a parallelism dimension to the search process by introducing multiple search elements operating concurrently on different partitions, transforming the single-threaded sequential examination into a multi-threaded parallel examination that achieves both speed and complexity management.
Data Source
AI summary
An invention is provided for parallel ECC error location in a memory. The invention includes partitioning a set of field elements into w partitions. Then, for each of the w partitions of field elements, i) providing a set of r different field elements of the partition to r parallel search element. Next, in operation ii), each parallel search element computes a sum that is based on a set of coefficients of an error locator polynomial and the field element provided to the particular parallel search element. The set of field elements is advanced r field elements in GF(2m), and operations i) through iii) are repeated using the next r different field elements of the partition.