Parallel BCH Encoding-Decoding for NOR Flash Error Correction
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Solution Overview
Problem
NOR flash memories face challenges in reliability due to high bit error rates and complex circuitry in error correcting codes, which are insufficient for modern nanoscale manufacturing processes, requiring a method for fully parallel encoding and decoding to accelerate speed and reduce circuit complexity.
Innovation Solution
The method involves factorizing a generator polynomial into minimal polynomials, deriving roots, and generating encoding matrices for parallel encoding and decoding, allowing for error correction with reduced hardware complexity and increased speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Bose-Chaudhuri-Hocquenghem (BCH) code is used to correct more than one error bit, then error correcting capacity is improved, but circuit complexity increases and decoding speed becomes insufficient
Solution Approach 1:
The patent segments the encoding and decoding processes into independent parallel units. The encoding process is divided into multiple encoding units that operate simultaneously on different data segments, while the decoding process is divided into syndrome calculation units, error location units, and error correction units that work in parallel. This segmentation enables high-speed operation without proportionally increasing overall circuit complexity.
Solution Approach 2:
The patent transitions from sequential processing to parallel processing by introducing a temporal dimension. Multiple encoding and decoding operations that would traditionally execute sequentially are transformed into simultaneous operations through the use of parallel processing units, achieving high-speed decoding while maintaining manageable circuit complexity through systematic organization.
2Reliability
If conventional error correcting codes are used, then reliability is improved, but encoding and decoding speed becomes slow
Solution Approach 1:
The patent performs preliminary actions by pre-calculating and storing syndrome values and error location patterns in lookup tables during the design phase. During actual encoding and decoding operations, these pre-computed values are quickly retrieved and combined with current data, significantly accelerating the process while maintaining robust error correction capability.
Solution Approach 2:
The patent divides the encoding and decoding functions into multiple independent parallel units that operate simultaneously. Each unit handles a specific portion of the error correction task, and their results are combined to achieve the complete error correction function, thereby increasing overall processing speed without sacrificing reliability.
3Quantity of substance
If manufacturing process is scaled down to nanoscale, then integration density is improved, but bit error rate increases
Solution Approach 1:
The patent merges the encoder and decoder circuits into a unified error correction code system that shares common computational resources and data pathways. This integration reduces the overall area required for error correction functionality while providing comprehensive error protection, thereby maintaining high integration density even at nanoscale manufacturing processes.
Data Source
AI summary
A memory system, a fully parallel encoding method, and a fully parallel decoding method are disclosed. The encoding method utilizes a plurality of minimal polynomials that constitute a generator polynomial to derive a plurality of roots from the minimal polynomials. A first encoding matrix derived according to the roots of the minimal polynomials is subsequently decomposed to derive a second encoding matrix, in which partial elements of the second encoding matrix are common in those of a parity check matrix of the decoder, such that the encoder and the decoder can efficiently share the same hardware. In addition, the decoding method defines a new error locator polynomial and utilizes a cubic matrix operation to respectively combine the equations, which reduces the hardware required by the fully parallel architecture.