Parallel BFP-to-BCD Conversion with Concurrent FPU Rounding

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Solution Overview

Problem

Conventional floating point units (FPUs) are inefficient as they perform conversion from binary floating point (BFP) to binary coded decimal (BCD) format sequentially, leading to idle cycles during the rounding process, which increases cycle time and processing latency.

Innovation Solution

Implementing a parallel conversion and rounding process within the FPU, where the conversion from BFP to BCD is performed concurrently with the rounding operation, decoupling the conversion from the wait time required for the rounding operation to complete.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If sequential conversion from BFP to BCD is performed, then conversion accuracy is maintained, but processing time increases due to idle cycles during rounding

Engineering Contradiction:

Improveconversion accuracyVSAvoidcycle time

Core Design Contradiction:

Measurement precisionVSLoss of time

Solution Approach 1:

The rounding operation is performed in parallel with the conversion operation, effectively preparing the rounding result in advance while the conversion is still in progress. This eliminates the sequential wait time where the converter would be idle, thereby reducing total cycle time without compromising conversion accuracy.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

By overlapping the rounding operation with the conversion operation, the system ensures that both operations are continuously executing without idle cycles. The converter remains busy converting BFP to BCD while the rounder simultaneously processes the rounding, maximizing resource utilization and reducing overall processing time.

Inventive Principle:

Principle #20Continuity of useful action

2Productivity

If parallel conversion and rounding are implemented, then processing efficiency increases, but device complexity increases

Engineering Contradiction:

Improveprocessing efficiencyVSAvoidFPU structure

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The FPU is divided into functionally independent modules: a converter unit for BFP to BCD conversion and a rounder unit for rounding operations. These segmented units can operate independently and in parallel, reducing interdependencies and enabling simultaneous execution without requiring complex coordination mechanisms.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

An intermediate register or buffer is introduced to hold the BFP value during parallel processing. This intermediary structure allows the converter and rounder to access the same input data simultaneously without conflict, simplifying the parallel architecture compared to implementing complex shared resource management.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS11221826B2Parallel rounding for conversion from binary floating point to binary coded decimal

Publication Date: 2022.01.11 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

Embodiments of the invention are directed to a computer-implemented method of for parallel conversion to binary coded decimal format. The method includes receiving, by a floating point unit (FPU), a value in binary floating point (BFP) format. The BFP value includes an integer part and a fractional part. The FPU converts the BFP value to a binary coded decimal (BCD) value. In parallel to converting the BFP value to a BCD value, the FPU performs a rounding operation on the BFP value. The FPU receives the rounding information and operates on the BCD value accordingly.