Parallel BIST Circuit Inspection for Reduced Test Time
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Solution Overview
Problem
The existing method of using a single BIST circuit for multiple inspection target circuits prolongs inspection time due to the need for sequential execution of inspections.
Innovation Solution
Implementing a plurality of BIST circuits connected to corresponding level inspection circuits and a combining unit that performs logical operations on their comparison results to generate a single inspection signal, allowing for parallel execution of BIST and level inspections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If one BIST circuit is used to inspect multiple inspection target circuits, then device complexity is reduced, but inspection time is prolonged due to sequential execution
Solution Approach 1:
The inspection system is segmented into multiple independent BIST circuits, each capable of independently inspecting a specific inspection target circuit. This segmentation enables parallel execution of inspections, resolving the contradiction by allowing multiple circuits to be inspected simultaneously rather than sequentially, thus reducing inspection time while maintaining reasonable device complexity through modular design
Solution Approach 2:
The inspection architecture transitions from a single-dimensional sequential inspection model to a multi-dimensional parallel inspection model. By introducing multiple BIST circuits operating in parallel across different inspection target circuits, the system adds a spatial dimension to the inspection process, enabling simultaneous inspections and significantly reducing total inspection time
2Loss of time
If multiple BIST circuits are used to inspect multiple inspection target circuits in parallel, then inspection time is reduced, but device complexity increases
Solution Approach 1:
The inspection system is divided into independent modular BIST circuit units, each responsible for a specific inspection target circuit. This segmentation allows parallel operation of multiple circuits while keeping each unit relatively simple, balancing the trade-off between reduced inspection time and increased device complexity through manageable modularity
Solution Approach 2:
Each BIST circuit is designed with universal functionality to perform both BIST inspections and level inspections on its designated inspection target circuit. This multi-functionality reduces the need for separate dedicated circuits for each inspection type, thereby limiting the increase in device complexity while achieving parallel inspection and reduced inspection time
3Reliability
If BIST inspection and level inspection are performed separately, then inspection thoroughness is improved, but inspection time is prolonged
Solution Approach 1:
The BIST inspection and level inspection functions are merged into a single integrated inspection process executed by each BIST circuit. The BIST circuit simultaneously performs BIST inspection on its inspection target circuit and level inspection on the connection between the BIST circuit and the target circuit, combining multiple inspection types into one unified operation that maintains thoroughness while reducing total inspection time through parallel execution
Solution Approach 2:
The level inspection of connection circuits is performed concurrently with the BIST inspection rather than sequentially after it. By executing the level inspection action in parallel alongside the BIST inspection, the system maintains comprehensive inspection coverage while reducing the total time required, as both inspection types proceed simultaneously rather than one waiting for the other to complete
Data Source
AI summary
An inspection apparatus includes a plurality of BIST circuits, each BIST circuit being configured to compare a test pattern output from an inspection target circuit with an expected value and output a signal indicating a comparison result, and a combining unit configured to generate one signal by performing a logical operation on a plurality of the signals indicating the comparison results which are output from the plurality of BIST circuits. The combining unit includes a plurality of level inspection circuits each configured to perform a level inspection of detecting a stuck-at fault. Each of the plurality of BIST circuits is connected to a corresponding one of the plurality of level inspection circuits.