Parallel Bit Counting in Array Statistics Processing
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Solution Overview
Problem
Existing methods for calculating array statistics in computer memory using CPU resources are inefficient, particularly when requiring bit-level operations, as they involve serial processing and extensive operations per word, leading to high processing times.
Innovation Solution
A system and method utilizing a processor to operate on n-bit wide words, where counters are arranged vertically in memory, allowing for parallel bit counting and carry propagation through XOR and AND operations, significantly reducing the number of operations needed by processing multiple bits simultaneously.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If traditional serial bit-level operations are used to calculate array statistics, then processing accuracy is maintained, but processing time increases significantly
Solution Approach 1:
The patent segments the bit-counting operation into multiple parallel stages using a tree-structured counter array. Each stage processes a portion of the bits simultaneously, dividing the single-threaded serial operation into multi-threaded parallel operations that can be executed concurrently, thereby reducing overall processing time while maintaining accuracy.
Solution Approach 2:
The patent transitions from a one-dimensional serial processing approach to a two-dimensional parallel processing architecture by organizing counters in a vertical array structure where multiple counters operate simultaneously on different bit positions. This dimensional change enables parallel execution of bit-counting operations across multiple CPU cores or processing units.
2Productivity
If vertical counter array structure is used, then parallel processing capability is improved, but memory access pattern complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-organizing the counter array in a vertical structure with counters arranged by bit significance positions before processing begins. This pre-arranged structure enables systematic memory access patterns where consecutive memory locations correspond to consecutive bit positions, simplifying the access pattern complexity despite the parallel processing requirements.
3Productivity
If n-bit wide word operations are used, then operations per word are reduced, but the number of required counters increases
Solution Approach 1:
The patent merges multiple individual bit-counting operations into a unified parallel counter array structure. By combining the functionality of multiple counters into a single vertical array that processes n-bit words simultaneously, the system reduces the effective number of operations per word while distributing the counting function across multiple counter elements that work in parallel rather than sequentially.
Data Source
AI summary
The present disclosure describes systems and techniques relating to calculation of array statistics. According to an aspect of the described systems and techniques, a device includes: a memory configured to store a data array and a counter array, wherein the data array includes multiple values, and each of the multiple values is encoded in a respective row of the data array, and wherein the counter array includes multiple counters, respective columns of the counter array correspond to respective ones of the counters, and rows of the counter array correspond with bit significance positions spanning the multiple counters; and processor electronics configured to add up a number bits found in respective columns of the data array using respective ones of the multiple counters.