Parallel Bit Interleaver Layout for QC-LDPC Folding Sections
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing bit-interleaved coding and modulation systems with quasi-cyclic low-density parity-check codes face inefficiencies in interleaving codewords, leading to suboptimal performance due to impaired parallelism and limited bit interleaver configurations, especially when the number of cyclic blocks is not a multiple of the bit interleaver's columns.
Innovation Solution
A bit interleaving method that divides codewords into constellation words by applying a bit permutation process, selecting a subset of cyclic blocks such that their number is a multiple of the divisor M, and mapping bits from multiple cyclic blocks to each constellation word, ensuring efficient interleaving and improved parallelism.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional bit interleaving is applied to QC-LDPC codewords, then the interleaving process can be performed, but parallelism is impaired and bit interleaver configurations are limited when the number of cyclic blocks is not a multiple of the interleaver columns
Solution Approach 1:
The codeword is divided into multiple cyclic blocks, and the bit interleaver is configured with a number of columns that is a divisor of the number of cyclic blocks. This segmentation allows the interleaving process to be divided into multiple independent parallel operations, improving both efficiency and adaptability.
Solution Approach 2:
The invention changes the parameter of the bit interleaver from a fixed column configuration to a configurable column number that is a divisor of the cyclic block count. This parameter change enables the interleaver to adapt to different codeword sizes and cyclic block configurations, resolving the contradiction between flexibility and efficiency.
2Adaptability or versatility
If the number of cyclic blocks is not a multiple of the bit interleaver columns, then various configurations can be supported, but parallelism is impaired leading to suboptimal performance
Solution Approach 1:
By defining the bit interleaver column count as a divisor of the cyclic block count rather than requiring a fixed relationship, the system achieves both configuration compatibility and optimal parallelism. This parameter redefinition allows any number of cyclic blocks to be supported while maintaining full parallelism.
Solution Approach 2:
The bit interleaver configuration becomes dynamic rather than static, adapting its column count based on the actual number of cyclic blocks in the codeword. This dynamic configuration ensures that parallelism is always maximized regardless of the specific codeword size or cyclic block count.
3Ease of operation
If traditional interleaving methods are used, then the process is simpler to implement, but latency is increased and parallelism is reduced
Solution Approach 1:
The interleaving process is segmented into multiple parallel column operations, where each column can be processed independently and simultaneously. This segmentation reduces the overall latency by executing multiple operations in parallel rather than sequentially, while maintaining implementation simplicity through the regular structure of the bit interleaver.
Data Source
AI summary
A bit interleaving method involves applying a bit permutation process to bits of a QC-LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword after the permutation process into a plurality of constellation words each including M bits, the codeword being divided into F×M′/M folding sections (N′ being a subset of N selected cyclic blocks and being a multiple of M/F), each of the constellation words being associated with one of the F×M′/M folding sections, and the bit permutation process being applied such that each of the constellation words includes F bits from each of M/F different cyclic blocks in a given folding section associated with a given constellation word.