Parallel Bit Interleaving for QC-LDPC Folding Sections
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Solution Overview
Problem
Existing bit-interleaved coding and modulation systems with quasi-cyclic low-density parity-check codes face inefficiencies in interleaving, particularly when the number of cyclic blocks is not a multiple of the bit interleaver's columns, leading to impaired parallelism and increased latency, especially in iterative decoding processes.
Innovation Solution
A bit interleaving method that divides codewords into folding sections, applying a bit permutation process to map M bits from multiple cyclic blocks into constellation words, ensuring all bits in a folding section are mapped to only Q/F constellation words, thereby optimizing interleaving and reducing latency while enhancing parallelism.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional bit interleaving is applied to QC-LDPC codes, then the interleaving process can be completed, but parallelism is impaired and latency increases when the number of cyclic blocks is not a multiple of the interleaver columns
Solution Approach 1:
The patent divides the codeword into multiple folding sections, where each folding section contains a specific number of cyclic blocks. This segmentation allows the interleaving process to be organized into manageable units that can be processed in parallel, resolving the issue of impaired parallelism when the total number of cyclic blocks is not a multiple of the interleaver columns.
Solution Approach 2:
The patent introduces a folding factor F that creates an additional dimension in the interleaving structure. By organizing bits into folding sections and using the folding factor to determine how many cyclic blocks are grouped together, the system transforms the traditional single-dimension interleaving into a multi-dimensional structure that enables better parallel processing and reduces latency.
2Adaptability or versatility
If the number of cyclic blocks is not a multiple of the interleaver columns, then the interleaving can accommodate arbitrary code lengths, but parallelism is impaired
Solution Approach 1:
The patent employs a dynamic folding factor F that can be adjusted based on the specific code length and interleaver configuration. This dynamic parameter allows the system to adapt to different code lengths while maintaining optimal parallelism by flexibly grouping cyclic blocks into folding sections, ensuring that the interleaving structure remains efficient regardless of whether the total number of cyclic blocks is a multiple of the interleaver columns.
Data Source
AI summary
A bit interleaving method involves applying a bit permutation process to a QC-LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword after the permutation process into a plurality of constellation words each including M bits, the codeword being divided into F×N/M folding sections, each of the constellation words being associated with one of the F×N/M folding sections, and the bit permutation process being applied such that each of the constellation words includes F bits from each of M/F different cyclic blocks in a given folding section associated with a given constellation word.