Parallel Bit Interleaving for QC-LDPC Decoding Latency
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Solution Overview
Problem
Existing bit-interleaved coding and modulation systems with quasi-cyclic low-density parity-check codes face inefficiencies in interleaving, particularly when the number of cyclic blocks is not a multiple of the bit interleaver's columns, leading to impaired parallelism and increased latency, especially in iterative decoding processes.
Innovation Solution
A bit interleaving method that divides codewords into constellation words with specific bit permutation and selection processes, ensuring that each constellation word includes bits from multiple cyclic blocks, allowing for efficient interleaving and improved parallelism by selecting a subset of cyclic blocks that are multiples of the number of bits per constellation, thereby optimizing interleaving and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional bit interleaving is applied to QC-LDPC codewords, then the interleaving process can be performed, but parallelism is impaired and latency increases when the number of cyclic blocks is not a multiple of the interleaver columns
Solution Approach 1:
The codeword is divided into multiple cyclic blocks, and the bit interleaving process is segmented into multiple stages corresponding to different cyclic blocks. This segmentation allows independent processing of each cyclic block, enabling parallel execution when the number of cyclic blocks is a multiple of the interleaver columns, thereby improving productivity without increasing latency.
2Productivity
If the number of cyclic blocks is increased to improve parallelism, then more bits can be processed in parallel, but the system complexity increases
Solution Approach 1:
The invention changes the parameter of the number of cyclic blocks to be a multiple of the interleaver columns. This parameter adjustment enables full utilization of the interleaver's parallel processing capability without requiring additional hardware resources or increasing system complexity, as the same interleaver structure can handle any codeword length by adjusting the number of cyclic blocks.
3Reliability
If bit permutation is applied to all cyclic blocks, then complete interleaving is achieved, but processing time increases due to sequential handling of non-multiple blocks
Solution Approach 1:
The codeword is pre-organized into a specific number of cyclic blocks that is a multiple of the interleaver columns before the bit permutation process. This preliminary organization ensures that the subsequent bit permutation can be applied to all cyclic blocks in parallel without sequential processing delays, achieving complete interleaving without increased processing time.
Data Source
AI summary
A bit interleaving method involves applying a bit permutation process to bits of a QC-LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword after the permutation process into a plurality of constellation words each including M bits, the codeword being divided into F×N′/M folding sections (N′ being a subset of N selected cyclic blocks and being a multiple of M/F), each of the constellation words being associated with one of the F×N′/M folding sections, and the bit permutation process being applied such that each of the constellation words includes F bits from each of M/F different cyclic blocks in a given folding section associated with a given constellation word.