Parallel Bit Interleaving for QC-LDPC Latency and Parallelism
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Solution Overview
Problem
Existing bit-interleaved coding and modulation (BICM) systems with quasi-cyclic low-density parity-check codes face inefficiencies in interleaving, particularly when the number of cyclic blocks in the LDPC codeword is not a multiple of the number of columns in the bit interleaver matrix, leading to impaired parallelism and increased latency, especially in iterative decoding.
Innovation Solution
A bit interleaving method that applies a bit permutation process to quasi-cyclic low-density parity-check codes, dividing the codeword into constellation words and performing intra-cyclic-block permutations to optimize the mapping of bits onto constellations, ensuring each constellation word is associated with multiple cyclic blocks and mapped efficiently across sections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional bit interleaving is applied to QC-LDPC codes, then the interleaving process can be completed, but parallelism is impaired and latency increases when the number of cyclic blocks is not a multiple of the number of columns
Solution Approach 1:
The patent segments the bit interleaving process into two distinct stages: (1) a bit permutation process applied to the entire codeword, and (2) an intra-cyclic-block permutation process applied to each cyclic block individually. This segmentation allows the system to handle cases where the number of cyclic blocks is not a multiple of the number of columns, maintaining parallelism while completing the interleaving process efficiently.
Solution Approach 2:
The patent introduces dynamic adaptation by making the intra-cyclic-block permutation configurable and adjustable. The system can dynamically select different permutation strategies based on the relationship between the number of cyclic blocks and the number of columns, optimizing parallelism and reducing latency for different code configurations.
2Productivity
If conventional bit interleaving is applied to QC-LDPC codes, then the interleaving process can be completed, but parallelism is impaired
Solution Approach 1:
By dividing the interleaving into two independent permutation stages, the patent enables each stage to be implemented in a parallel-friendly manner. The bit permutation process operates on the entire codeword structure, while the intra-cyclic-block permutation operates independently on each cyclic block, allowing for parallel processing across multiple blocks without complex coordination requirements.
Solution Approach 2:
The patent applies the bit permutation process as a preliminary action before the intra-cyclic-block permutation. This preliminary reorganization of bits creates a structured intermediate state that facilitates subsequent parallel intra-cyclic-block permutations, reducing the complexity of achieving parallelism in the overall interleaving process.
Data Source
AI summary
A bit interleaving method applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks of Q bits each, dividing the processed codeword into constellation words of M bits each, and applying an intra-cyclic-block permutation process to the cyclic blocks, where the codeword is divided into F×N/M folding sections of M/F cyclic blocks each and the constellation words are each associated with one of the folding sections, and the bit permutation process is applied such that the constellation words are each made up of F bits from each of M/F different cyclic blocks in the associated section, after the permutation process.