Parallel Bit Interleaving for QC-LDPC Folding Sections
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Solution Overview
Problem
Existing bit-interleaved coding and modulation systems with quasi-cyclic low-density parity-check codes face inefficiencies in interleaving, particularly when the number of cyclic blocks is not a multiple of the bit interleaver's columns, leading to impaired parallelism and increased latency, and limited bit interleaver configurations.
Innovation Solution
A bit interleaving method that divides codewords into folding sections, applying a bit permutation process to map M bits from multiple cyclic blocks into constellation words, ensuring all bits in a folding section are mapped to only Q/F constellation words, thereby optimizing interleaving and reducing latency while enhancing parallelism.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional bit interleaving is applied to QC-LDPC codes, then the interleaving process can be performed, but parallelism is impaired and latency increases when the number of cyclic blocks is not a multiple of the interleaver columns
Solution Approach 1:
The patent divides the codeword into multiple folding sections, where each folding section contains a specific number of cyclic blocks. This segmentation allows the interleaving process to be organized into manageable units that can be processed in parallel, resolving the contradiction by creating structured segments that maintain parallelism while handling arbitrary numbers of cyclic blocks.
Solution Approach 2:
The patent introduces a folding dimension by organizing cyclic blocks into folding sections with a folding factor. This dimensional reorganization transforms the interleaving structure from a single-dimensional column-based approach to a multi-dimensional structure, enabling parallel processing across folding sections and eliminating the constraint that cyclic blocks must be a multiple of interleaver columns.
2Adaptability or versatility
If conventional bit interleaving is applied to QC-LDPC codes, then the interleaving process can be performed, but the number of available bit interleaver configurations is limited
Solution Approach 1:
The patent introduces a configurable folding factor that dynamically adjusts the number of folding sections and cyclic blocks per section. This dynamic parameter allows the interleaver to adapt to different code lengths and transmission requirements without changing the fundamental interleaver structure, thereby increasing configuration flexibility while maintaining a consistent device architecture.
Solution Approach 2:
The patent creates a universal interleaver structure that can handle various QC-LDPC code configurations through the folding mechanism. By using folding sections and a configurable folding factor, a single interleaver design can serve multiple functions and accommodate different numbers of cyclic blocks, eliminating the need for multiple specialized interleaver configurations.
Data Source
AI summary
A bit interleaving method involves applying a bit permutation process to a QC-LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword after the permutation process into a plurality of constellation words each including M bits, the codeword being divided into F×N/M folding sections, each of the constellation words being associated with one of the F×N/M folding sections, and the bit permutation process being applied such that each of the constellation words includes F bits from each of M/F different cyclic blocks in a given folding section associated with a given constellation word.