Parallel Bit Test Circuit for Semiconductor Memory Devices
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Solution Overview
Problem
Conventional parallel bit test methods for semiconductor memory devices are inefficient as they test memory banks sequentially, leading to extended test times and increased costs due to the difficulty in increasing the number of channels, which affects the reliability and productivity of highly-integrated devices.
Innovation Solution
A semiconductor memory device and method that allows for simultaneous testing of two or more memory banks using a test unit and flag signal generator to perform independent logic operations and compare results, reducing test time and providing error information for each bank.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If sequential testing of memory banks is performed using conventional parallel bit test methods, then device complexity is reduced, but test time increases and productivity decreases
Solution Approach 1:
The test circuit is segmented into multiple independent test units, each capable of testing a specific memory bank. Each test unit includes dedicated logic operation circuits (XOR/XNOR) and control circuits that can operate independently on different memory banks simultaneously, enabling parallel testing without requiring a single complex centralized test circuit.
Solution Approach 2:
Multiple test units are merged into a single test system that shares common control signals and data buses. The test units are combined in such a way that they can be controlled simultaneously through unified control circuits while maintaining independent operation capabilities, achieving parallel testing without proportionally increasing control complexity.
2Loss of time
If the number of test channels is increased to test multiple memory banks in parallel, then test time is reduced, but device complexity and manufacturing cost increase
Solution Approach 1:
Each test unit is designed with universal functionality to handle multiple memory banks. The logic operation circuits and control circuits within each test unit can be configured to test different memory banks through programmable control signals, allowing a smaller number of multi-functional test units to replace a larger number of single-purpose channels.
Solution Approach 2:
The patent introduces a time dimension to the testing process by implementing time-multiplexed control signals. Control signals are transmitted in different time slots to different test units, enabling multiple test units to be controlled through a reduced number of physical control channels, thus reducing the dimension of control complexity while maintaining parallel testing capability.
3Reliability
If conventional parallel bit test logic circuits are used for each memory bank, then testing accuracy is maintained, but test time increases due to sequential operation
Solution Approach 1:
Data is pre-loaded into multiple memory banks before the parallel testing operation begins. The test control circuits are pre-configured with the necessary control signals for each test unit. This preliminary preparation allows all test units to commence testing simultaneously without waiting for sequential data preparation or control signal generation, thereby maintaining accuracy while improving efficiency.
Solution Approach 2:
The patent ensures continuous useful action by implementing simultaneous logic operations across all test units. While conventional methods perform logic operations sequentially on each memory bank, this invention maintains continuous operation across all test units in parallel, with each unit continuously performing read, compare, and evaluate operations on its assigned memory bank without interruption or waiting for other units to complete.
Data Source
AI summary
An integrated circuit device includes a test circuit and at least one flag generator circuit. The test circuit is configured to generate first and second sets of test results in parallel in response to a memory test operation. The first and second sets of test results respectively correspond to first and second memory banks. The test circuit is further configured to merge respective ones of the first set of test results with respective ones of the second set of test results to provide a set of merged test results to respective ones of a set of output terminals of the integrated circuit device. The at least one flag generator circuit is configured to generate a first flag signal that indicates a presence of at least one memory test error in the first set of test results, and a second flag signal that indicates a presence of at least one memory test error in the second set of test results. Based on the set of merged test results and the first and second flag signals, the test circuit may determine which of the memory blocks of the first and second memory banks includes a defective memory cell therein. Related methods are also discussed.