Parallel Bit Test Circuit for Semiconductor Memory Defect Detection
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Solution Overview
Problem
Conventional parallel bit test methods in semiconductor memory devices are limited in detecting defective memory cells due to fixed bit comparisons and a restricted range of test patterns, which can fail to identify correlated defects within the same memory block and may not detect all defective cells.
Innovation Solution
A parallel bit test circuit and method that includes primary and secondary comparators to compare bits within the same memory block in one mode and between different memory blocks in another mode, expanding the range of test data patterns to improve defect detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fixed bit comparisons within the same memory block are performed, then the test circuit structure is simple, but the test coverage is limited and correlated defects cannot be detected
Solution Approach 1:
The patent implements dynamic test modes that can switch between intra-block comparison (first test mode) and inter-block comparison (second test mode). The test circuit dynamically reconfigures its operation based on the selected mode, allowing the same circuit to perform different comparison functions without requiring separate dedicated circuits for each test type.
Solution Approach 2:
The test circuit is designed with universal comparators that can perform multiple functions: comparing bits within the same memory block (first test mode) and comparing bits from different memory blocks (second test mode). This multi-functionality increases defect detection capability while avoiding the need for separate specialized circuits.
2Reliability
If a restricted range of test patterns is used, then the test process is simple and fast, but defective cells cannot be fully identified
Solution Approach 1:
The patent employs dynamic test patterns that can be selectively applied based on the test mode. In the first test mode, one set of test patterns is used for intra-block comparison, while in the second test mode, different test patterns are applied for inter-block comparison. This dynamic pattern selection ensures comprehensive defect coverage without requiring all possible patterns to be applied sequentially.
Solution Approach 2:
The test system performs preliminary selection of appropriate test patterns based on the chosen test mode before actual testing begins. This preliminary action ensures that the most relevant test patterns are applied first, improving defect detection efficiency without requiring exhaustive testing with all possible patterns.
3Reliability
If only intra-block bit comparisons are performed, then the test circuit operation is simple, but correlated defects within the same block are not detected
Solution Approach 1:
The patent implements a dynamic test architecture that can switch between two test modes: first test mode for intra-block comparisons and second test mode for inter-block comparisons. The circuit dynamically reconfigures data routing and comparator operations based on the selected mode, enabling detection of both random and correlated defects without requiring permanently complex circuitry.
Solution Approach 2:
The patent extends the test dimension from within-block comparison to between-block comparison. By adding the dimension of inter-block data routing and comparison, the system can detect correlated defects that manifest across different memory blocks while using the same basic comparator circuitry through reconfigured data paths.
Data Source
AI summary
A semiconductor memory device performs a parallel bit test on a plurality of memory blocks by writing test pattern data into the plurality of memory blocks, outputting two bits from each memory block in parallel and comparing the two bits output from each memory block with each other in a first test mode, and outputting two bits from respectively different memory blocks and comparing the two bits output from the respectively different memory blocks with each other in a second test mode.