Parallel Bit Test Circuit Switching Unit for Semiconductor Memory
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Solution Overview
Problem
Conventional semiconductor memory device manufacturing processes face challenges in efficiently identifying and replacing defective memory cells, which prolongs the testing time and increases production costs due to the need for serial bit testing.
Innovation Solution
The implementation of a parallel bit test circuit that uses a switching unit to transfer and combine test result data from multiple memory banks, allowing for the output of twice as many data bits during a single read operation cycle, thereby reducing test time and enhancing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If serial bit testing is used to identify defective memory cells, then the testing process is simpler, but the testing time is significantly prolonged
Solution Approach 1:
The patent merges multiple test result data streams from different memory banks into a single output bus using a switching unit. This combining approach allows parallel testing of multiple memory cells simultaneously while utilizing a unified output path, thereby increasing testing speed without proportionally increasing output circuit complexity
Solution Approach 2:
The patent employs a dynamic switching unit that can reconfigure its connection topology based on the testing phase. The switching unit dynamically connects different input buses to the output bus, enabling flexible data routing that supports both parallel testing operations and simplified output handling, thus resolving the contradiction between speed and complexity
2Loss of time
If parallel bit test circuit is implemented to reduce testing time, then the testing speed increases, but the device complexity increases
Solution Approach 1:
The patent segments the memory array into multiple banks that can be tested in parallel, with each bank having its own comparison and latch units. The switching unit further segments the data flow by selectively connecting different bank outputs to the shared output bus. This segmentation enables simultaneous testing of multiple banks, reducing overall testing duration while managing complexity through modular organization
Solution Approach 2:
The switching unit serves multiple functions: it routes test result data from different memory banks, enables parallel testing operations, and provides a unified interface to the output bus. This multi-functionality allows the circuit to achieve parallel testing capabilities without requiring separate dedicated output paths for each bank, thereby reducing the overall complexity increase
3Productivity
If multiple test result data bits are output simultaneously, then the testing efficiency improves, but the data bus complexity increases
Solution Approach 1:
The patent combines multiple data streams from different memory banks into a single unified output bus through the switching unit. This merging approach allows simultaneous output of multiple test result data bits while utilizing a single data bus infrastructure, thereby improving testing efficiency without requiring multiple separate output buses and their associated complex routing
Data Source
AI summary
Parallel bit test circuits for use in a semiconductor memory devices are provided which include a first bus that has N bus lines that are configured to transfer a first group of N bits of test result data and a second bus that has N bus lines that are configured to transfer a second group of N bits of test result data. These parallel bit test circuits further include a switching unit that has a plurality of unit switches, where each switch is configured to connect a bus line of the first bus and a respective bus line of the second bus in response to a switching control signal that is applied after the second group of N bits of test result data are output from the second bus, to transfer the first group of N bits of test result data from the first bus to the second bus so as to output a total of 2N bits of test result data through the second bus.