Parallel Bit Test Circuit for Memory Bank Testing
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Solution Overview
Problem
Current memory device testing methods are inefficient in evaluating large memory regions, leading to prolonged development periods and statistical limitations due to the need for serial testing, which can miss non-repairable banks and result in failed chips being processed as good.
Innovation Solution
A memory device with an evolved parallel bit test (PBT) circuit that includes sense amplifiers, comparators, and logic circuits to perform parallel testing, allowing for the comparison of data bits with test bits and passing banks regardless of test results using a test pass signal, thereby skipping non-repairable regions and masking their output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If serial testing is used, then testing thoroughness is improved, but testing time increases significantly
Solution Approach 1:
The memory device is divided into multiple banks that can be tested independently and in parallel. Each bank is tested separately using dedicated sense amplifiers and comparators, allowing simultaneous testing of multiple segments rather than sequential testing of the entire memory device.
Solution Approach 2:
The testing approach transitions from serial (one-dimensional sequential testing) to parallel (multi-dimensional simultaneous testing) by introducing multiple testing paths through different banks. This dimensional change allows multiple test operations to occur concurrently, dramatically reducing total test time while maintaining thoroughness.
2Productivity
If parallel bit test is implemented, then testing speed is improved, but ability to identify and handle non-repairable banks deteriorates
Solution Approach 1:
The memory device is divided into multiple banks that can be tested independently and in parallel. Each bank is tested separately using dedicated sense amplifiers and comparators, allowing simultaneous testing of multiple segments rather than sequential testing of the entire memory device.
Solution Approach 2:
The logic circuit receives test results from all comparators and provides feedback to determine the overall pass/fail status. This feedback mechanism ensures that even in parallel testing, the system can accurately identify which banks failed and make appropriate decisions about chip qualification.
3Reliability
If all banks must pass test to qualify chip, then quality control is improved, but yield decreases due to non-repairable banks
Solution Approach 1:
The patent applies different quality standards to different regions (banks) of the memory device. Non-repairable banks can be identified and excluded from the pass/fail decision, while repairable banks must still meet quality standards. This local quality approach allows chips with some defective banks to be salvaged through repair, improving yield without compromising overall quality.
Solution Approach 2:
The system identifies non-repairable banks and discards them from the pass/fail evaluation, while recovering value from chips by repairing defective banks using redundant resources. This allows chips that would otherwise be rejected to be salvaged, improving yield while maintaining quality control through selective evaluation.
4Loss of time
If development period is shortened through faster testing, then time to market is improved, but statistical limitations increase
Solution Approach 1:
The testing approach transitions from serial (one-dimensional sequential testing) to parallel (multi-dimensional simultaneous testing) by introducing multiple testing paths through different banks. This dimensional change allows multiple test operations to occur concurrently, dramatically reducing total test time while maintaining statistical validity through comprehensive coverage.
Solution Approach 2:
The patent performs preliminary identification of non-repairable banks before final pass/fail determination. This preliminary action allows the testing system to focus resources on repairable banks and avoid wasting time on irreparable defects, thereby shortening the overall development period without compromising statistical validity of the testing process.
Data Source
AI summary
A memory device includes: a plurality of sense amplifier circuits sensing a data bit in response to a parallel test signal from a plurality of banks; a plurality of comparators comparing the data bit from each of the plurality of sense amplifier circuits with a test bit; and a logic circuit receiving output signals of the plurality of comparators and outputting a test result, wherein each of the plurality of comparators receives the test bit, an evolved parallel bit test (PBT) signal, at least one test ignore signal, and a test pass signal, and compares the data bit and the test bit in response to the evolved parallel bit test (PBT) signal, the at least one logic state test setting signal, and the test pass signal, and passes a corresponding bank regardless of a test operation in response to the test pass signal.