Parallel Bitline Nonvolatile Memory with Channel-Based Processing
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Solution Overview
Problem
Current non-volatile memory technologies, such as NAND and NOR types, face challenges in achieving optimal program/erase times and read times simultaneously, with NAND having fast program and erase speeds but slow read times, and NOR providing fast read speeds but slower program and erase speeds, limiting the scalability and reliability of digital memory.
Innovation Solution
A parallel bitline semiconductor architecture coupled with a channel-based operating process that enables single-cell access for program and read operations, utilizing electron or hole tunneling over a channel region to increase threshold voltage and inhibit programming in adjacent cells, resulting in fast and scalable memory with reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If NAND-type semiconductor memory is used, then program and erase speeds are improved, but read times become slow
Solution Approach 1:
The memory device is segmented into two distinct memory arrays: a first memory array using NAND-type semiconductor memory optimized for program and erase operations, and a second memory array using NOR-type semiconductor memory optimized for read operations. This segmentation allows each array to specialize in its respective function, resolving the contradiction between fast program/erase speeds and fast read times.
Solution Approach 2:
The memory device achieves multi-functionality by integrating both NAND and NOR memory types within a single device structure. The controller intelligently directs program and erase operations to the NAND array while directing read operations to the NOR array, enabling the device to provide both fast program/erase performance and fast read performance simultaneously.
2Speed
If NOR-type semiconductor memory is used, then read speed is improved, but program and erase speeds become slow
Solution Approach 1:
The memory device is segmented into two distinct memory arrays: a first memory array using NAND-type semiconductor memory optimized for program and erase operations, and a second memory array using NOR-type semiconductor memory optimized for read operations. This segmentation allows each array to specialize in its respective function, resolving the contradiction between fast program/erase speeds and fast read times.
Solution Approach 2:
The memory device achieves multi-functionality by integrating both NAND and NOR memory types within a single device structure. The controller intelligently directs program and erase operations to the NAND array while directing read operations to the NOR array, enabling the device to provide both fast program/erase performance and fast read performance simultaneously.
3Quantity of substance
If memory density is increased, then data storage capacity is improved, but scalability and reliability become limited
Solution Approach 1:
The memory device is segmented into two distinct memory arrays: a first memory array using NAND-type semiconductor memory optimized for program and erase operations, and a second memory array using NOR-type semiconductor memory optimized for read operations. This segmentation allows each array to specialize in its respective function, resolving the contradiction between fast program/erase speeds and fast read times.
Solution Approach 2:
The memory device achieves multi-functionality by integrating both NAND and NOR memory types within a single device structure. The controller intelligently directs program and erase operations to the NAND array while directing read operations to the NOR array, enabling the device to provide both fast program/erase performance and fast read performance simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution provides a memory device with improved read performance, program/erase performance, and increased scalability, achieving faster, more reliable, and power-efficient operations while maintaining high data retention and reliability.
Implementation Method 1
employing a channel-based operating process that utilizes electron or hole tunneling over a channel region to increase a threshold voltage of a program cell
Implementation Method 2
employing a channel-based operating process that utilizes electron or hole tunneling over a channel region to increase a threshold voltage of a program cell
Implementation Method 3
one or more other wordlines adjacent to the associated wordline can be raised to an intermediate voltage, thereby boosting voltage of inhibited bitlines through capacitive coupling
Data Source
AI summary
Various aspects provide for a new combination of non-volatile memory architecture and memory processing technology. A memory cell has a gate node, a source node and a drain node. The gate node is connected to a wordline of the memory, the source node is connected to a local source line of the memory, and the drain node is connected to a local data line of the memory. A channel-based processing component programs the memory cell and inhibits programming of a second memory cell on the wordline of the memory. The channel-based processing component also grounds the local source line and the local data line in conjunction with programming the memory cell, and floats a second local source line and a second local data line connected to the second memory cell in conjunction with inhibiting programming of the second memory cell.