Parallel Block Invalidate Stream Processing for Multi-CPU Cache Coherence
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Solution Overview
Problem
In multi-processor systems, block invalidate operations are time-consuming and can lead to delays, as they require serial execution and may not ensure immediate access to updated data, causing CPUs to retrieve old data from caches unless a block invalidate operation is completed.
Innovation Solution
Implementing a method that performs a range check on each CPU access during a block invalidate operation, treating cache hits within the invalidate range as cache misses to ensure data is retrieved from main memory, and allowing concurrent execution of overlapping block invalidate, block writeback, and block writeback and invalidate requests to reduce waiting time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If block invalidate operations are executed serially to ensure cache coherence, then data correctness is maintained, but processing time increases and system productivity decreases
Solution Approach 1:
The patent segments the block invalidate operation into multiple independent parallel streams, where each stream processes a portion of the cache sets. Multiple block invalidate operations can execute simultaneously in different streams, dividing the overall operation into concurrent tasks that reduce total execution time while maintaining coherence through stream management.
Solution Approach 2:
The patent introduces a new dimension of parallel execution by implementing multiple independent invalidate streams that can process different cache sets simultaneously. This transforms the single-threaded serial invalidate operation into a multi-dimensional parallel processing system, effectively increasing throughput without sacrificing data correctness.
2Reliability
If CPUs wait for block invalidate operations to complete before accessing cached data, then data correctness is ensured, but access delay increases
Solution Approach 1:
The patent implements preliminary action by checking whether a cache access falls within an invalidate range before the invalidate operation completes. If the access is within the range, the system proactively treats it as a cache miss and retrieves data from main memory in advance, eliminating the need for CPUs to wait for invalidate completion while ensuring data correctness.
Solution Approach 2:
The system implements feedback by monitoring ongoing invalidate operations and using this information to make real-time decisions about cache access handling. When a CPU access request is received during an invalidate operation, the system checks the invalidate range and provides feedback to determine whether to treat the access as a hit or miss, optimizing both correctness and performance.
3Reliability
If multiple overlapping block invalidate operations are executed serially, then resource conflicts are avoided, but execution time increases due to waiting
Solution Approach 1:
The patent segments multiple overlapping block invalidate operations into separate parallel streams, allowing them to execute simultaneously rather than serially. Each stream handles a portion of the invalidate work, and the system manages resource allocation across streams to prevent conflicts while maintaining high utilization of cache resources.
Solution Approach 2:
The patent merges multiple overlapping invalidate operations into parallel execution streams, combining resources and processing capacity to handle multiple operations concurrently. This merging approach allows the system to process overlapping ranges in parallel while maintaining correctness through coordinated stream management.
Data Source
AI summary
A method to eliminate the delay of multiple overlapping block invalidate operations in a multi CPU environment by overlapping the block invalidate operation with normal CPU accesses, thus making the delay transparent. The cache controller performing the block invalidate operation merges multiple overlapping requests into a parallel stream to eliminate execution delays. Cache operations other that block invalidate, such as block write back or block write back invalidate may also be merged into the execution stream.