Parallel Boot-Strap Processor Memory Initialization
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Solution Overview
Problem
Conventional computing systems are inefficient in initializing memory, with approximately 90% of the initialization time consumed by memory training, and they can only leverage multiple processors after system memory initialization is complete, limiting early-stage processing capabilities.
Innovation Solution
Implementing a multithread, parallel processing computing platform using enhanced firmware that executes a boot-strap processor and application processors in parallel before system memory initialization, utilizing cross-reference circuitry to redirect memory requests and store instructions in cache memory for faster execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional sequential initialization is used, then system stability is maintained, but initialization time is excessively long and processing capability is underutilized
Solution Approach 1:
The patent performs memory initialization actions in advance by executing initialization code from cache memory before system memory is fully initialized. The bootstrap processor loads and executes initialization routines from cache memory, allowing memory training and other initialization tasks to begin before the memory initialization process completes, thus reducing overall initialization time.
Solution Approach 2:
The patent introduces a new execution dimension by implementing multithreaded parallel processing where the bootstrap processor and application processors operate simultaneously. The BSP executes initialization code while APs perform other tasks, creating parallel execution paths that eliminate sequential bottlenecks and improve initialization throughput.
2Loss of time
If memory training is performed sequentially, then memory initialization accuracy is ensured, but 90% of initialization time is consumed by this single process
Solution Approach 1:
The system loads memory initialization and training code into cache memory in advance, allowing the memory training process to start before system memory initialization completes. This preliminary preparation enables overlapping of memory training with the memory initialization process, reducing the critical path time.
Solution Approach 2:
The patent maintains continuous useful action by ensuring that while the bootstrap processor performs memory training, application processors simultaneously execute other initialization tasks. This continuous parallel utilization of processing resources eliminates idle time and maximizes productivity throughout the initialization phase.
3Productivity
If multiple processors are activated after memory initialization, then system reliability is maintained, but processing parallelism is delayed
Solution Approach 1:
The cache memory serves as an intermediary that enables application processors to execute initialization code before system memory is fully initialized. By using cache memory as the execution medium rather than system memory, the system allows multiple processors to operate in parallel during initialization while maintaining system stability through the use of already-initialized cache memory.
Data Source
AI summary
A computing device that implements a multithread parallel processing computing platform prior to initialization of system memory is provided. To implement this platform, the computing device executes enhanced firmware that defines a plurality of application processors (APs) under the control of a boot-strap processor (BSP). The BSP preserves backward compatibility of the APs by configuring cross-reference circuitry (e.g., a programmable attribute map) to reroute memory access requests generated by the APs that are addressed to a wakeup buffer to a redirected memory address. Memory at the redirected memory address stores AP initialization instructions and instructions to retrieve and process early stage process instructions stored elsewhere (e.g., in fast access cache memory). The APs, in parallel, execute the initialization instructions and the early stage process instructions stored in cache to complete an early stage process, such as memory training.