Parallel Buffer Signal Multiplexing for High Data Rates
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Solution Overview
Problem
Conventional signal-multiplexing devices face limitations in handling increased data rates due to parasitic resistance and capacitance from serially connected transfer gates, which blunt the output waveform and restrict the frequency band.
Innovation Solution
A signal-multiplexing device with M pre-stage buffers and an output buffer that outputs input signals based on combinations of control signals, using tri-state buffers and switches to manage signal levels and timings, reducing parasitic effects and enhancing data rate handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If two transfer gates are connected in series to multiplex signals, then the allowable range of delay time is widened and data rate handling is improved, but parasitic resistance and capacitance increase causing waveform blunting and frequency band limitation
Solution Approach 1:
The patent divides the signal path into multiple parallel segments (multiple buffers B1 to Bm) instead of using a single serial path. Each buffer operates independently with its own transfer gates, allowing signals to be multiplexed through parallel processing rather than serial chaining, thereby reducing cumulative parasitic effects while maintaining data rate handling capability
Solution Approach 2:
The patent introduces an intermediate selection mechanism using control signals (Cm and Cn) that mediate which buffer output is connected to the final output. This intermediary switching approach avoids the need for long serial chains of transfer gates, reducing parasitic accumulation while achieving the same signal multiplexing function
2Adaptability or versatility
If serial connection of transfer gates is used for signal multiplexing, then signal switching capability is achieved, but output waveform is blunted and frequency band is limited
Solution Approach 1:
The signal multiplexing function is segmented across multiple parallel buffers rather than achieved through a single serial chain. Each buffer maintains signal integrity independently, and the parallel architecture prevents the cumulative waveform degradation that occurs in serial connections
Solution Approach 2:
The patent transitions from a one-dimensional serial connection architecture to a two-dimensional parallel architecture with multiple buffers operating simultaneously. This dimensional change allows signal switching capability to be maintained while avoiding the waveform blunting inherent in serial connections
Data Source
AI summary
A signal-multiplexing device according to the present embodiment has a structure that is capable of satisfactorily handling an increase in a data rate. The signal-multiplexing device includes M pre-stage buffers and an output buffer. An m-th pre-stage buffer Bm outputs an m-th input signal when the signal levels of both an m-th control signal Cm and an n-th control signal Cn of M control signals are significant, and the m-th pre-stage buffer Bm enters into a high-impedance state when the signal level of at least one of the m-th control signal Cm and the n-th control signal Cn is non-significant. The output buffer Bout sequentially outputs input signals that have been respectively outputted from the M pre-stage buffers at different timings.