Parallel Bus Interface Circuit for Memory Bandwidth
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Solution Overview
Problem
Traditional computing systems with serial data transmission between host devices and memory apparatuses face limitations in expanding data bandwidth and signal integrity as frequency increases, requiring additional circuits like SerDes for data conversion.
Innovation Solution
The proposed computing system architecture employs a host, memory controller, interface circuit, and memory apparatus connected through multiple buses with varying data widths and clock rates, enabling parallel data communication and reducing the need for additional data conversion circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If serial data transmission is used to minimize the number of data signal transmission lines, then the number of transmission lines is reduced, but additional SerDes circuits are required increasing device complexity
Solution Approach 1:
The system is divided into distinct functional modules: host device, memory controller, interface circuit, and memory apparatus. Each module has dedicated data buses with specific widths optimized for their function, eliminating the need for complex SerDes circuits while maintaining efficient data transmission
Solution Approach 2:
The patent transitions from serial data transmission (one-dimensional time-based communication) to parallel data transmission using multi-width data buses (multi-dimensional spatial communication). This allows multiple data bits to be transmitted simultaneously across multiple transmission lines, reducing the need for conversion circuits
2Productivity
If the width of the second data bus is made greater than or equal to the width of the first data bus, then data bandwidth is increased, but the architecture becomes more complex
Solution Approach 1:
Different segments of the data path have locally optimized bus widths matched to their specific requirements. The first data bus has width W1 optimized for host-controller communication, while the second data bus has width W2 optimized for interface-memory communication, allowing each segment to operate at optimal efficiency without requiring the entire system to be upgraded
Solution Approach 2:
The architecture allows for dynamic scaling of bus widths at different interface points. The interface circuit can handle variable data widths from W1 to W2, enabling the system to adapt to different performance requirements and memory capacities without fundamental redesign
3Productivity
If advanced packaging technologies increase the number of signal transmission lines, then data bandwidth can be expanded, but the host device and memory apparatus must be manufactured as chiplets increasing manufacturing complexity
Solution Approach 1:
The system is segmented into separate chiplets (host device, memory controller, interface circuit, memory apparatus) that can be manufactured independently using standard processes, then packaged together with the required number of transmission lines to achieve the desired bandwidth without requiring complex monolithic manufacturing
Solution Approach 2:
The interface circuit acts as an intermediary component that bridges the host device and memory apparatus. This intermediary can be implemented as a separate chiplet that simplifies the manufacturing process by providing a standardized interface layer, making it easier to integrate different chiplets with varying transmission line requirements
Data Source
AI summary
A computing system may include a memory controller, an interface circuit, and a memory apparatus. The interface circuit may perform parallel data communication with the memory controller as well as with the memory apparatus. A clock rate of a bus between the interface circuit and the memory controller may be greater than or equal to a clock rate of a bus between the interface circuit and the memory apparatus.