Parallel Bus Phase Correction for Clock Data Alignment

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Solution Overview

Problem

Existing parallel bus data transmission systems face issues with phase offsets between the clock and data sequences due to inconsistencies in transmission delay and environmental changes, leading to communication errors and limited transmission frequency.

Innovation Solution

A method and device for parallel bus phase correction, which involves performing phase correction tests on both the clock and data lines using preset adjustment values to determine optimal windows and adjust the phase to ensure accurate data transmission, using a median value for optimal phase alignment.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the transmission frequency of the parallel bus is increased, then the data transmission speed is improved, but the phase offset between clock and data becomes more severe due to smaller clock periods

Engineering Contradiction:
Improvedata transmission speedVSAvoidphase alignment accuracy
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent performs phase correction tests in advance to determine optimal phase adjustment values for both clock and data lines before actual data transmission. This preliminary calibration ensures that even at high transmission frequencies where clock periods are small, the phase relationships are pre-optimized to prevent sampling errors.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent systematically varies phase adjustment parameters during testing, trying multiple preset phase adjustment values to identify the optimal configuration. By changing phase parameters and observing test results, the system adapts to the specific transmission characteristics of each bus line, enabling reliable high-speed operation.

Inventive Principle:
Principle #35Parameter changes

2Adaptability or versatility

If the data bus and clock line have different transmission delays due to PCB or cable limitations, then the physical design flexibility is improved, but sampling errors occur at the receiving end

Engineering Contradiction:
Improvephysical design flexibilityVSAvoidsampling accuracy
Core Design Contradiction:
Adaptability or versatilityVSMeasurement precision

Solution Approach 1:

The patent applies different phase adjustment values to different bus lines individually. Each data line and the clock line are tested and calibrated separately with their own optimal phase adjustment parameters, allowing the system to compensate for line-specific delay characteristics while maintaining overall system flexibility.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The system performs phase correction tests and uses the test results to determine optimal phase adjustment values. This feedback mechanism allows the system to identify and correct sampling errors caused by differential delays, ensuring accurate data reception despite physical design variations.

Inventive Principle:
Principle #23Feedback

3Adaptability or versatility

If environmental conditions such as temperature change, then the operational adaptability is improved, but the sequential relationship between clock and data becomes unstable

Engineering Contradiction:
Improveenvironmental adaptabilityVSAvoidsequential relationship stability
Core Design Contradiction:
Adaptability or versatilityVSStability of the object's composition

Solution Approach 1:

The patent performs phase correction tests in advance to establish optimal phase adjustment values that account for environmental variations. By pre-calibrating the system with margin for environmental changes, the sequential relationship remains stable even when temperature or other conditions vary during operation.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11789488B2Parallel bus phase correction method and device
Publication Date: 2023.10.17 INSPUR SUZHOU INTELLIGENT TECH CO LTD
  • US11789488B2 patent drawing
  • US11789488B2 patent drawing
  • US11789488B2 patent drawing

AI summary

A parallel bus phase correction method and a device are provided. The method comprises: correcting a data bus, respectively performing phase correction tests on a clock line; determining a first optimal window of the clock line according to the clock test results; correcting the clock line by using a median value of the first optimal window, respectively performing phase correction tests on the data bus according to the multiple second phase adjustment values, and recording corresponding data test results; determining a second optimal window of the data bus according to the data test results; and performing phase correction on normal data transmission on the basis of the median value of the first optimal window and the median value of the second optimal window. The method achieves phase correction and ensures the correctness and accuracy of data transmission, even if a small clock offset is present.