Parallel Busbar Design for Uniform Current Distribution in Semiconductor Modules

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Solution Overview

Problem

In semiconductor devices with multiple modules connected in parallel, differences in wiring length lead to variations in inductance and resistance, causing surge voltages and switching failures due to uneven current distribution across modules.

Innovation Solution

The semiconductor device employs busbars with specific resistance and inductance characteristics, ensuring that the largest resistance and inductance between the terminal and attachment portions are 10% or less of the corresponding values in the wiring portions, thereby minimizing current differences between modules.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If wiring lengths differ between parallel-connected semiconductor modules, then inductance differences occur, but surge voltages and switching failures result

Engineering Contradiction:
Improvewiring length flexibilityVSAvoidswitching operation stability
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

By positioning all attachment portions at equal distances from the terminal portion along the busbar, the design creates equipotential connection points that eliminate inductance differences. This ensures that even though modules may be physically distributed, their electrical paths remain equal, preventing surge voltages and switching failures.

Inventive Principle:
Principle #12Equipotentiality

2Reliability

If busbar resistance and inductance are reduced to 10% or less of wiring portion values, then current distribution uniformity improves, but busbar design complexity increases

Engineering Contradiction:
Improvecurrent distribution uniformityVSAvoidbusbar structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The busbar design specifies that resistance and inductance between the terminal portion and each attachment portion should be 10% or less of the corresponding values in the wiring portions. This parameter-based approach provides a clear design criterion that balances performance requirements with manufacturing feasibility, ensuring current distribution uniformity without excessive complexity.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration reduces the influence of busbar resistances and inductances, leading to more uniform current distribution and improved reliability and power cycle life of the semiconductor device.

Implementation Method 1

at least one busbar that includes one terminal portion and a plurality of attachment portions, which are connected to the main terminals, and connects the semiconductor modules in parallel

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Implementation Method 2

a largest resistance out of resistances between the terminal portion and the respective attachment portions is 10% or less of a resistance of the wiring portion

Methodology Applied
Scientific EffectElectrical resistance: Electrical Resistance

Implementation Method 3

a largest inductance out of inductances between the terminal portion and the respective attachment portions is 10% or less of an inductance of the wiring portion

Methodology Applied
Scientific EffectElectrical inductance: Inductor

Data Source

PatentUS9967991B2Semiconductor device and busbar
Publication Date: 2018.05.08 FUJI ELECTRIC CO LTD
  • US9967991B2 patent drawing
  • US9967991B2 patent drawing
  • US9967991B2 patent drawing

AI summary

A semiconductor device, including a plurality of semiconductor modules, each including a semiconductor element, a main terminal and a wiring portion that connects the semiconductor element and the main terminal, and at least one busbar that each includes a terminal portion, and a plurality of attachment portions, the attachment portions being respectively connected to the main terminals of the semiconductor modules, such that the at least one busbar connects the semiconductor modules in parallel. The largest resistance among all resistances between the terminal portion and each of the attachment portions in each busbar is 10% or less of a resistance of the wiring portion in each semiconductor module. The largest inductance among all inductances between the terminal portion and each of the attachment portions in each busbar is 10% or less of an inductance of the wiring portion in each semiconductor module.