Parallel Byte Error Position Circuit for Faster Reed-Solomon Correction
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Solution Overview
Problem
Existing byte error correction methods, particularly those using Reed-Solomon codes, are slow when correcting 2-byte errors in memory cells like MRAM and RRAM, necessitating a faster approach for parallel error correction to enhance data reliability.
Innovation Solution
A circuit arrangement is proposed to determine byte error position signals in parallel using components of an error syndrome, enabling rapid identification and correction of byte errors across multiple bytes, employing a t-byte-error-correcting code with (t+1) byte error position signals, and using Galois field multipliers for efficient error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Reed-Solomon code is used for correcting 2-byte errors in memory cells, then error correction capability is improved, but correction speed deteriorates
Solution Approach 1:
The error correction process is segmented into independent parallel operations. Instead of sequentially processing bytes to correct 2-byte errors, the invention divides the correction task into separate syndrome calculation units and correction units that operate simultaneously on different byte positions, achieving parallel processing while maintaining Reed-Solomon error correction capability
Solution Approach 2:
The invention pre-calculates and stores syndrome values in lookup tables before actual error correction is needed. By preparing syndrome information in advance and organizing it for rapid access, the system eliminates time-consuming syndrome calculations during the correction phase, significantly speeding up the error correction process while preserving the reliability of Reed-Solomon coding
2Speed
If parallel error correction is implemented for multiple bytes, then correction speed is improved, but device complexity increases
Solution Approach 1:
The invention designs universal correction units that can handle multiple byte positions using the same hardware structure. The syndrome calculation and correction logic are made multi-functional through lookup tables that provide syndrome values for all possible error patterns, allowing a single correction unit to serve multiple byte positions in parallel without requiring separate dedicated circuits for each byte
Solution Approach 2:
Instead of creating entirely new complex circuitry for parallel processing, the invention uses lookup tables that store pre-computed syndrome patterns. These tables act as templates that can be rapidly accessed and applied to multiple byte positions simultaneously, effectively copying the correction logic through data rather than through complex hardware replication
Data Source
AI summary
A circuit arrangement for determining in parallel of at least two byte error position signals for identifying at least one byte error in a binary sequence comprising a plurality of bytes, wherein the binary sequence in the error-free case is a code word of an error code, the circuit arrangement is configured such that each of the at least two byte error position signals is determinable using components of an error syndrome of the error code such that the components indicate whether or not a byte of the binary sequence that is associated with the byte error position signal is erroneous.