Parallel Byte Error Correction Using Locator Polynomial Values
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Solution Overview
Problem
Existing byte error correction methods, such as those using Reed-Solomon codes, are inefficient for correcting errors in multiple bytes simultaneously, particularly in memory cells like MRAM and RRAM, where fast error correction is crucial for data reliability.
Innovation Solution
A circuit arrangement is proposed that determines byte error position signals and correction values to correct at least one byte error in a binary sequence. This involves calculating first, second, and third values for each byte position based on the locator polynomial's coefficients, allowing for the correction of byte errors in a parallel manner.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Reed-Solomon code is used for byte error correction, then error correction capability is improved, but correction speed deteriorates
Solution Approach 1:
The error correction process is segmented into independent parallel operations for each byte position. Instead of processing bytes sequentially through a single Reed-Solomon decoder, the patent divides the correction into separate calculation paths that can operate simultaneously, with each path handling one byte position's correction value computation independently.
Solution Approach 2:
The patent transitions from sequential time-based processing to spatial parallel processing by introducing multiple calculation paths that operate simultaneously. This dimensional shift allows correction values for multiple bytes to be computed in parallel rather than one after another, effectively adding a spatial dimension to the correction process.
2Speed
If parallel error correction is implemented for multiple bytes, then correction speed is improved, but device complexity increases
Solution Approach 1:
The patent employs universal calculation units that can compute correction values for any byte position using the same algorithmic structure. Each calculation path uses identical components (multipliers, adders, constants) that are replicated and configured to handle different byte positions, reducing the need for specialized complex circuitry for each byte.
Solution Approach 2:
The patent manages complexity by changing parameters such as using pre-computed constants (a_L, a_2L) that are specific to each byte position but follow a systematic pattern. This allows the same computational structure to be reused with different parameter values rather than requiring entirely different circuits for each byte position.
Data Source
AI summary
An approach corrects at least one byte error in a binary sequence, the binary sequence comprising multiple bytes and being a codeword of an error code if there is no error. The approach comprises: (i) determining at least one byte error position signal indicating whether or not a byte of the binary sequence is erroneous, (ii) determining at least one byte error correction value on the basis of which an erroneous byte position identified by using the byte error position signal is able to be corrected, (iii) wherein the at least one byte error correction value is determined by determining a first value, a second value and a third value for each of at least three byte positions according to a coefficient of the locator polynomial, and (iv) correcting the at least one byte error on the basis of the at least one byte error correction value.