Parallel CABAC Coefficient Flag Decoding in One Clock Cycle
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Solution Overview
Problem
The computational complexity of the CABAC decoding process in the H.264/AVC video coding standard hinders encoding and decoding speed, and conventional approaches to address this issue involve increasing operational frequency, which is undesirable.
Innovation Solution
A CABAC decoding method and unit that detect and decode control signals to process multiple bins, including coefficient flags, in a single clock cycle, efficiently determining whether coefficient values are zero and if the coefficient map decoding process is finished, utilizing two decoders to update control signals and maintain continuous decoding without idle cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional CABAC decoding is used, then decoding accuracy is maintained, but decoding speed is hindered due to computational complexity
Solution Approach 1:
The patent divides the decoding of multiple bins into parallel segments by using multiple decoders (first decoder and second decoder) that operate simultaneously on different bins. This segmentation of the decoding process into parallel tasks reduces the overall computational complexity per clock cycle while maintaining decoding accuracy, directly addressing the contradiction between speed and complexity.
Solution Approach 2:
The patent introduces a temporal dimension by utilizing multiple clock cycles to decode different bins in parallel across time. By organizing the decoding process to handle multiple bins across different time slots with multiple decoders, the system achieves higher throughput without increasing the complexity of individual decoding operations, thus improving speed while managing complexity.
2Productivity
If operational frequency is increased to handle computational complexity, then decoding speed improves, but hardware operational frequency requirements increase
Solution Approach 1:
The patent merges multiple decoding operations into a single clock cycle by using multiple decoders that work in parallel. Instead of increasing the frequency of a single decoder, the system combines multiple decoding functions simultaneously, achieving higher productivity (decoding efficiency) without raising the operational frequency of the hardware, thus resolving the contradiction between productivity and operational frequency.
Solution Approach 2:
The patent prepares and organizes multiple decoding operations to be executed in parallel within the same clock cycle. By pre-arranging the decoding tasks and allocating multiple decoders to handle different bins simultaneously, the system achieves efficient throughput without requiring higher operational frequencies, as the work is distributed across multiple units rather than accelerated in a single unit.
3Productivity
If multiple bins are decoded in one clock cycle, then decoding speed increases, but the complexity of coordinating multiple decoders increases
Solution Approach 1:
The patent segments the bitstream into different bin sequences that can be independently decoded by multiple decoders. Each decoder handles a specific portion of the decoding task with clear boundaries and dependencies, reducing the coordination complexity while maintaining high throughput. The segmentation allows parallel processing without requiring complex inter-decoder communication and control logic.
Data Source
AI summary
A context-based adaptive binary arithmetic coding (CABAC) method. The CABAC method for a bitstream comprises: detecting a control signal (Sig_first); decoding a first bin representing one of a first coefficient flag (Sig) and a second coefficient flag (Last) from the bitstream according to the control signal (Sig_first); decoding a second bin representing one of the second coefficient flag (Last) and a next first coefficient flag (Sig) from the bitstream according to the decoded first bin and the control signal (Sig_first); and updating the control signal (Sig_first) according to the decoded first and second bins. The first and second bins are decoded in one clock cycle, the first coefficient flag (Sig) indicates whether a corresponding coefficient value is zero, and the second coefficient flag (Last) indicates whether a coefficient map decoding process is finished.