Parallel Calibration Circuit for High-Frequency Impedance Adjustment
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Solution Overview
Problem
Conventional calibration circuits struggle to perform sufficient impedance adjustments in output buffers when faced with high-frequency external clocks, leading to reduced calibration steps and inadequate impedance updates, especially when the number of clock divisions increases, resulting in insufficient calibration operations.
Innovation Solution
A calibration circuit design that performs parallel calibration operations for both pull-up and pull-down replica buffers in response to a first calibration command, allowing for sufficient impedance updates even at high external clock frequencies, and alternates calibration operations between the two replica buffers in response to a second command.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the number of clock divisions is increased to handle high external clock frequencies, then the external clock frequency can be accommodated, but the number of adjustment steps performed during calibration period is reduced
Solution Approach 1:
The calibration circuit is divided into two independent replica buffers (first replica buffer for pull-up circuit and second replica buffer for pull-down circuit) that operate simultaneously. This segmentation allows the calibration operations to be performed in parallel, effectively doubling the number of adjustment steps without increasing the calibration period or requiring additional clock cycles.
Solution Approach 2:
By performing calibration operations for both pull-up and pull-down circuits simultaneously through parallel operation of two replica buffers, the useful action of impedance adjustment is continuous and maximized throughout the calibration period, rather than alternating between circuits which would create idle time.
2Device complexity
If conventional sequential calibration is used for pull-up and pull-down circuits, then circuit complexity is reduced, but sufficient calibration operation cannot be performed at high clock frequencies
Solution Approach 1:
The calibration operations for pull-up and pull-down circuits are merged into a single simultaneous process by using two replica buffers that operate in parallel. This combining of operations maintains relatively simple circuit structures while ensuring sufficient calibration performance even at high external clock frequencies.
3Use of energy by moving object
If the first adjustment step uses the final code from previous calibration, then power consumption is reduced, but the number of actual impedance updates is reduced by one
Solution Approach 1:
The calibration process is segmented into two independent parallel processes (first replica buffer and second replica buffer), so that even if one buffer skips an update, the other buffer performs the update, ensuring that the total number of impedance updates is maintained.
Solution Approach 2:
By having two replica buffers that are copies of each other performing the same calibration function in parallel, the system ensures that if one replica misses an impedance update, the other replica compensates by performing the update, thereby maintaining the total number of updates.
Data Source
AI summary
To include a first replica buffer that has substantially the same circuit configuration as a pull-up circuit which constitutes an output buffer and a second replica buffer that has substantially the same circuit configuration as a pull-down circuit which constitutes the output buffer. When a first calibration command ZQCS is issued, both a control signal ACT1 and ACT2 is activated, and a calibration operation is performed for both the first replica buffer and the second replica buffer in parallel.