Parallel Capacitor Structure for Low-Bias Image Sensor Capacitance
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Solution Overview
Problem
There is a demand for capacitative elements in stacked image sensors with low bias dependence and high capacitance density without reducing the operating voltage, as existing solutions face challenges in miniaturization and increased manufacturing costs.
Innovation Solution
A semiconductor device comprising a first capacitative element and a second capacitative element with opposite bias characteristics connected in parallel, utilizing a combination of MOS, MIM, MOM, and PIP capacitative elements to achieve increased capacitance density and reduced bias dependence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the capacitance density of a capacitative element is increased by reducing film thickness, then the capacitance value increases, but the TDDB (Time Dependent Dielectric Breakdown) deteriorates and product life shortens
Solution Approach 1:
The patent combines multiple types of capacitative elements (MOS capacitative element and MIM capacitative element) into a single integrated capacitative element structure. This merging allows the element to achieve high capacitance density through the MIM portion while the MOS portion maintains lower stress on the insulating film, thereby preserving product life without sacrificing capacitance performance
Solution Approach 2:
The capacitative element uses a composite structure combining MOS (Metal-Oxide-Semiconductor) and MIM (Metal-Insulator-Metal) capacitative elements. This composite approach leverages the high capacitance density of MIM elements while using MOS elements to reduce overall stress on the insulating film, preventing TDDB deterioration and extending product life
2Quantity of substance
If the capacitance density is increased by increasing the dielectric constant, then the capacitance value increases, but the manufacturing cost increases
Solution Approach 1:
The patent merges MOS and MIM capacitative elements into a single structure that can be manufactured using standard CMOS processes. This combination achieves high capacitance density through the MIM portion without requiring exotic high-k dielectric materials, thereby maintaining manufacturing cost effectiveness while delivering the desired capacitance performance
3Quantity of substance
If the wiring space is reduced to increase capacitance density in comb-shaped wiring capacitative elements, then the capacitance density increases, but the TDDB of the insulating film deteriorates and product life shortens
Solution Approach 1:
The patent combines MOS and MIM capacitative elements where the MIM element provides the necessary capacitance density without requiring reduced wiring spaces. The MOS element structure inherently stresses the insulating film less, and when combined with MIM, achieves high capacitance density while maintaining adequate wiring space and insulating film integrity, thereby preserving product life
4Quantity of substance
If the film thickness of the insulating film is reduced to increase capacitance density, then the capacitance value increases, but the operating voltage must be lowered which is not acceptable
Solution Approach 1:
The capacitative element uses a composite structure combining MOS and MIM capacitative elements. The MIM portion provides high capacitance density with thicker insulating films that can sustain higher operating voltages, while the MOS portion contributes additional capacitance without requiring thin film structures. This composite approach achieves high capacitance density while maintaining the ability to operate at standard voltages
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for a significant increase in capacitance density while maintaining the operating voltage, reducing bias dependence and extending the product life by canceling out bias characteristics, thus enabling the creation of high-performance capacitative elements for image sensors.
Implementation Method 1
a first capacitative element stacked on the semiconductor substrate; and a second capacitative element which is stacked on an opposite side to a side of the semiconductor substrate of the first capacitative element and of which a capacitance value has bias characteristics being opposite to bias characteristics of a capacitance value of the first capacitative element
Implementation Method 2
while a comb-shaped wiring capacitative element is an element which utilizes a parasitic capacitance formed by arranging wirings so as to oppose each other as a capacitative element
Implementation Method 3
incident light is received by the sensor portion and the incident light is photoelectrically converted inside the sensor portion by a photodiode
Data Source
AI summary
A semiconductor device capable of realizing a capacitative element of which a capacitance value has low bias dependence and of which capacitance density is high without lowering operating voltage is provided. The semiconductor device includes: a semiconductor substrate; a first capacitative element stacked on the semiconductor substrate; and a second capacitative element which is stacked on an opposite side to a side of the semiconductor substrate of the first capacitative element and of which a capacitance value has bias characteristics being opposite to bias characteristics of a capacitance value of the first capacitative element, wherein the first capacitative element and the second capacitative element are connected in parallel.