Parallel Capacitor Electrode Area Compensation for High Frequency Output
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional parallel capacitors in high frequency semiconductor devices exhibit differences in simultaneous-operation capacities between capacitors on the ends and center, leading to phase shifts and reduced output power due to unequal coupling and fringing capacities, resulting in decreased high frequency output power.
Innovation Solution
A parallel capacitor design with a dielectric substrate having both ends and a center portion, where the upper electrodes on the ends have a smaller area and thickness than those in the center, ensuring that the single-operation capacity of end capacitors is smaller than center capacitors, thereby equalizing simultaneous-operation capacities during parallel operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If all capacitors in the parallel capacitor have equal area upper electrodes, then the structure is simple and easy to manufacture, but the simultaneous-operation capacities differ between end and center capacitors due to coupling and fringing effects, causing phase shifts and reduced output power
Solution Approach 1:
The patent applies local quality by making the upper electrodes of end capacitors smaller than those of center capacitors. Specifically, the end upper electrodes have an area that is 0.5 to 0.8 times the area of center upper electrodes. This local differentiation compensates for the coupling and fringing effects that are more pronounced at the ends, thereby equalizing the simultaneous-operation capacities across all capacitors while maintaining manufacturing simplicity.
2Quantity of substance
If the spacing between upper electrodes is reduced to increase capacity, then the coupling capacity increases, but the fringing capacity becomes more significant, worsening the capacity imbalance between end and center capacitors
Solution Approach 1:
The patent addresses this contradiction by implementing local quality through differentiated upper electrode areas. When spacing between electrodes is reduced, the end upper electrodes are made smaller (0.5 to 0.8 times the center electrode area) to compensate for increased coupling and fringing effects. This local adjustment maintains capacity uniformity across the parallel capacitor while allowing reduced spacing to achieve higher overall capacity.
3Device complexity
If the parallel capacitor uses equal-area upper electrodes for all capacitors, then the design is simple, but the phase shifts occur during simultaneous operation, reducing the high frequency output power
Solution Approach 1:
The patent resolves this contradiction by applying local quality through non-uniform upper electrode areas. The end upper electrodes are designed with smaller areas (0.5 to 0.8 times the center electrode area) to compensate for coupling and fringing effects. This simple geometric modification equalizes the simultaneous-operation capacities, eliminates phase shifts during parallel operation, and maximizes high frequency output power without increasing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces the difference in simultaneous-operation capacities, minimizing phase shifts and enhancing high frequency output power by ensuring equal simultaneous-operation capacities across all capacitors, thus improving the output characteristics of high frequency semiconductor devices.
Implementation Method 1
an electric line of force E extends up to the neighboring capacitor 2011c on one side of the capacitor 2011e to which the high frequency is applied and so-called coupling occurs, generating a coupling capacity Ce-cup
Implementation Method 2
the electric line of force E swells in an outer direction on the other end of the capacitor 2011e to which the high frequency is applied, generating a so-called fringing capacity Ce-fringe
Data Source
AI summary
Certain embodiments provide a parallel capacitor including a substrate configured by a dielectric, upper electrodes, and a lower electrode. The upper electrodes are provided in an upper electrode region on a surface of the substrate. The lower electrode is provided on an entire surface of a lower electrode region including a region corresponding to the upper electrode region of an underside of the substrate, the lower electrode region being wider than the region. A single-operation capacity of each capacitor on both ends is smaller than the single-operation capacity of a capacitor in a center portion. The capacitors on the both ends are configured by the upper electrodes arranged on both ends of the substrate, the lower electrode, and the substrate. The capacitor in the center portion is configured by the upper electrode arranged in a center portion of the substrate, the lower electrode, and the substrate.