Parallel Capacitors in Array Substrate Compensation Circuit
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Solution Overview
Problem
Existing display panels face challenges in achieving high pixel values and increased storage capacitor capacitance simultaneously due to the large size of storage capacitors, which limits the number of pixels and display definition.
Innovation Solution
The array substrate design includes parallel capacitors formed by interconnecting gate metal, source-drain metal electrodes, and capacitive metal through vias, allowing for increased capacitance without expanding pixel size, achieved by positioning these metals above a polycrystalline silicon channel region and using buffer layers to maintain compactness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the size of the storage capacitor is increased to maintain potential stability, then the capacitance increases, but the pixel size increases which limits the number of pixels and display definition
Solution Approach 1:
The storage capacitor is divided into multiple parallel capacitors (first capacitor and second capacitor) that share common electrodes. By segmenting the capacitor structure and connecting them in parallel, the total capacitance is increased while the area occupied in the pixel is optimized, resolving the contradiction between capacitance size and pixel size.
Solution Approach 2:
Multiple capacitors are merged in parallel configuration with shared electrodes (first electrode and second electrode). This merging approach increases the total capacitance value without proportionally increasing the pixel area, as the capacitors share common structural elements and space.
2Manufacturing precision
If the number of pixels is increased to achieve high definition, then the display definition improves, but the pixel size decreases which reduces the space available for storage capacitors
Solution Approach 1:
The capacitor structure extends into the vertical dimension with multiple metal layers (first metal layer, second metal layer, third metal layer) and buffer layers. By utilizing the third dimension (vertical stacking), the capacitor achieves sufficient capacitance value without occupying excessive horizontal pixel area, enabling high pixel density while maintaining capacitor performance.
Solution Approach 2:
The capacitor structure is nested within the pixel circuit architecture, with capacitor electrodes integrated alongside transistor components. The first electrode, second electrode, and associated buffer layers are positioned to utilize available space efficiently, nesting the capacitor function within the overall pixel structure rather than adding separate dedicated space.
Data Source
AI summary
The present disclosure provides an array substrate, including: a base substrate, a first metal, a buffer layer, a second metal, a second buffer layer, a third metal. A via is defined in the first buffer layer and the second buffer layer to electrically interconnect the first metal and the third metal, so that the first metal, the second metal and the third metal constitute parallel capacitors.