Parallel CCD Clock Delay Lines for Fine Phase Control
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Solution Overview
Problem
Existing clock manager circuits provide limited granularity in clock phase shifts and are constrained by maximum operation frequency, which is inadequate for devices like FPGAs that require multiple modules with different clock phases.
Innovation Solution
The clock management circuit employs counter-controlled delay devices (CCDs) in parallel connections with latches and frequency dividers to allow independent control of phase and duty cycle, reducing the number of CCDs needed and increasing the maximum frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If counter controlled delay devices are placed in series to achieve less granularity, then phase control granularity is improved, but maximum operation frequency is limited by the intrinsic delay of the delay block
Solution Approach 1:
The delay block is segmented into multiple counter controlled delay devices (CCDs) that can be independently controlled. Each CCD can be individually enabled or disabled through separate control signals, allowing the total delay to be divided into finer granular segments while maintaining high operating frequency capability.
Solution Approach 2:
The invention introduces dynamic control mechanisms where control signals can selectively enable or disable specific CCDs based on the desired delay requirement. This dynamic configuration allows the system to adapt between fine granularity (when multiple CCDs are enabled) and high speed (when fewer CCDs are enabled), resolving the contradiction between precision and speed.
2Adaptability or versatility
If multiple delay blocks are used to provide different phase intervals, then phase coverage is improved, but device complexity increases
Solution Approach 1:
Each counter controlled delay device is designed to be multi-functional, capable of providing different delay amounts based on control signal inputs. A single CCD can serve multiple phase intervals by dynamically adjusting its delay, eliminating the need for separate dedicated delay blocks for each phase interval and reducing overall device complexity.
Solution Approach 2:
The invention changes the delay parameter of each CCD dynamically through control signals rather than requiring fixed delay blocks for each phase. By varying the control parameters (enable signals, count values), the same hardware structure can cover multiple phase intervals, reducing the number of physical delay blocks needed.
Data Source
AI summary
A clock manager circuit includes a number of clock output blocks, each providing an independent output. Counter controlled delay devices (CCDs) are used in these clock output blocks. To achieve full cycle delays, the CCDs are placed in parallel with outputs of the CCD outputs driving set and reset terminals of a common latch. The parallel connection of the CCDs, as opposed to a series connection, offers an increase in maximum frequency and possibly fewer needed CCDs than if the CCDs are placed in series. In one embodiment, at least one of the CCDs includes a counter/compare circuit with a frequency divider enabling the frequency of the CCD to be varied relative to the common input clock.