Data Transfer Controller with Parallel Channel Pipelining

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Solution Overview

Problem

Existing data transfer controllers are heavily coupled to external memory types, limiting flexibility and scalability, and lack concurrent transfer capabilities, making them inefficient for handling multiple peripherals and memory interchanges.

Innovation Solution

A data transfer controller with a hub and ports architecture that features uniform pipelining, supports multiple identical external ports, enables concurrent transfers across multiple channels, and includes a dedicated queue RAM for managing transfer requests, allowing for flexible interchanging of peripherals and memory without affecting the controller's operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If traditional data transfer controller architecture is used, then the controller can handle data transfers, but it is heavily coupled to external memory types which limits flexibility and scalability

Engineering Contradiction:

Improveflexibility and scalabilityVSAvoidcoupling to external memory types

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The controller is divided into separate functional modules: hub unit, channel registers, source control pipeline, destination control pipeline, and routing unit. Each module handles specific tasks independently, reducing interdependencies and coupling to external memory types while maintaining overall functionality.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The hub and ports architecture provides uniform pipelining that can handle multiple external memory types and peripheral devices through a standardized interface. The controller can freely interchange peripherals and memory without affecting operation, achieving universality across different device types.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Productivity

If sequential transfer processing is used, then the controller structure is simpler, but it lacks concurrent transfer capabilities making it inefficient for handling multiple peripherals

Engineering Contradiction:

Improveconcurrent transfer capabilitiesVSAvoidcontroller structure

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

Multiple independent channels (N channels) are implemented, each capable of handling transfers independently. The channel registers and control pipelines are segmented to process multiple transfers concurrently, enabling parallel operation without requiring a monolithic complex structure.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The controller adds temporal dimension to transfer processing by implementing pipelining across multiple stages (source control, destination control, routing). This allows transfers to progress through different stages simultaneously, achieving concurrent processing capability.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Adaptability or versatility

If uniform pipelining with multiple identical ports is implemented, then scalability and flexibility are improved, but the device complexity increases

Engineering Contradiction:

Improveinterchanging peripherals and memoryVSAvoidhub and ports architecture

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

M identical external ports are implemented with uniform interfaces and pipelining logic. Each port can serve as source or destination and can be freely interchanged without affecting controller operation, achieving universality that simplifies the overall system despite the multiple components.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

All M ports are made identical in structure and function, using the same pipelining logic and control mechanisms. This homogeneity reduces the complexity of managing diverse port types while maintaining scalability and flexibility.

Inventive Principle:

Principle #33Homogeneity

4Productivity

If dedicated queue RAM is added for managing transfer requests, then transfer management efficiency is improved, but memory usage and device complexity increase

Engineering Contradiction:

Improvetransfer request managementVSAvoiddedicated queue RAM

Core Design Contradiction:

ProductivityVSQuantity of substance

Solution Approach 1:

Transfer requests are queued in dedicated queue RAM before being processed by the control pipelines. This preliminary queuing organizes requests in advance, allowing the controller to manage transfers efficiently without requiring additional memory during active transfer operations.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS7546391B2Direct memory access channel controller with quick channels, event queue and active channel memory protection

Publication Date: 2009.06.09 TEXAS INSTRUMENTS INC

AI summary

A data transfer control apparatus includes a channel controller and a transfer controller. The channel controller receives, prioritizes and queues event signals and predetermined memory writes which trigger data transfer requests controlling the transfer controller. The event queue stores event numbers mapped to parameter memory locations storing data transfer parameters. The mapping table and the parameter memory are writeable via a memory mapped write operation. Memory protection registers store data indicative of permitted data accesses to the memory map.