Parallel Chase Decoding Circuit for High-Throughput Error Correction

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Solution Overview

Problem

Conventional Chase decoding methods for error correction in optical transmission systems with gigabit speeds struggle to achieve desired throughput due to sequential trial operations, necessitating an increase in decoding speed.

Innovation Solution

An error correction device that extracts hard decision values from soft decision sequences and performs parallel simulated correction operations using test patterns, including parallel test pattern selection, addition, syndrome calculation, and error correction, to enhance decoding speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If sequential trial operations are performed using test patterns in conventional Chase decoding, then error correction beyond algebraic decoding limit is achieved, but decoding speed decreases and throughput cannot meet gigabit transmission requirements

Engineering Contradiction:
Improveerror correction capabilityVSAvoiddecoding speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent segments the sequential trial operations into multiple parallel processing paths. Each path independently performs test pattern generation, addition, and syndrome calculation for different error patterns simultaneously. This segmentation of the decoding process into parallel segments resolves the contradiction by maintaining comprehensive error correction trials while executing them concurrently rather than sequentially, thereby achieving both high reliability and high speed decoding for gigabit transmission systems

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic parallel processing where multiple test patterns are generated and applied simultaneously across different data streams. The system dynamically manages multiple syndrome calculators and error pattern generators that operate in parallel, adapting the number and type of test patterns based on the received signal characteristics. This dynamic approach allows the system to maintain robust error correction while achieving the throughput required for gigabit optical transmission

Inventive Principle:
Principle #15Dynamics

2Measurement precision

If multiple test patterns are applied sequentially to achieve desired error correction, then correction accuracy improves, but decoding time increases

Engineering Contradiction:
Improvecorrection accuracyVSAvoiddecoding time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent applies preliminary action by pre-generating multiple test patterns and preparing parallel processing paths before the actual decoding operation. The system pre-configures multiple syndrome calculators and error pattern generators with different test patterns, so that when decoding is required, all corrections can be evaluated simultaneously rather than sequentially. This preliminary preparation of multiple correction paths maintains high correction accuracy while dramatically reducing the decoding time required to evaluate all possibilities

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent creates multiple copies of the test pattern generation and syndrome calculation functionality, operating in parallel. Instead of one sequential trial, the system generates copies of the decoding logic that simultaneously test different error patterns. Each copy independently processes the received sequence with its assigned test pattern, and the results are combined to determine the most likely original data. This copying approach preserves correction accuracy by thoroughly testing multiple hypotheses while reducing decoding time through parallel execution

Inventive Principle:
Principle #26Copying

Data Source

PatentUS20260005708A1Error correction device, error correction method, and control circuit
Publication Date: 2026.01.01 MITSUBISHI ELECTRIC CORP
  • US20260005708A1 patent drawing
  • US20260005708A1 patent drawing
  • US20260005708A1 patent drawing

AI summary

An error correction device includes a hard decision value extraction unit that extracts a hard decision value from a soft decision received-sequence containing soft decision information, and outputs, as a hard decision received-sequence, a hard decision value sequence that has been extracted; a test pattern position candidate selection unit that determines, on the basis of the soft decision information, test pattern position candidates, which are each a position of application of a test pattern to the hard decision received-sequence; and a simulated correction operation unit that performs, in parallel, generation of multiple test patterns to be applied at the test pattern position candidates, and error correction operations using the test patterns generated, on the hard decision received-sequence.