Parallel Chien Search Circuit for NAND Flash Error Decoding
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Solution Overview
Problem
The size and power consumption of arithmetic circuits used for decoding error correction codes, particularly in memory systems like NAND flash, increase significantly due to the Chien search method for calculating error positions, which is inefficient for handling varying error numbers.
Innovation Solution
The implementation of a parallel Chien search with two-division parallelism in the error position calculation unit, utilizing first and second substitution circuits to handle error correction codes efficiently by dividing the calculation into two parts based on the number of errors, reducing circuit size and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the Chien search method is used to calculate error positions using the error locator polynomial, then decoding accuracy is improved, but the size of the arithmetic circuit increases significantly
Solution Approach 1:
The error locator polynomial is divided into two parts: a first polynomial containing terms with even powers of x and a second polynomial containing terms with odd powers of x. This segmentation allows the arithmetic circuit to process each polynomial separately, reducing the overall circuit size while maintaining the ability to accurately determine error positions through combined evaluation of both polynomials.
2Measurement precision
If the Chien search method is used to calculate error positions, then decoding accuracy is improved, but power consumption increases
Solution Approach 1:
By dividing the error locator polynomial into two separate polynomials (even and odd power terms), the circuit performs fewer simultaneous operations and reduces the number of active circuit components at any given time, thereby lowering power consumption while still achieving accurate error position detection through combined polynomial evaluation.
3Adaptability or versatility
If a full error locator polynomial is used for Chien search, then all error scenarios are handled, but the circuit becomes inefficient for varying error numbers
Solution Approach 1:
The segmented polynomial structure enables the circuit to efficiently handle varying error numbers by selectively evaluating only the necessary terms from each polynomial based on the specific error scenario, improving decoding efficiency while maintaining comprehensive error scenario coverage through the combined capability of both polynomials.
Data Source
AI summary
In an arithmetic circuit, a first substitution circuit calculates p/2 first evaluation values by using a first input polynomial having first-order to s-th-order coefficients of the error locator polynomial. When the number of errors is t/2 or less, the arithmetic circuit outputs p pieces of information including: error position information calculated from the first evaluation values obtained by substituting p/2 first check values, and error position information calculated from a second evaluation values obtained by substituting the first check values into a second input polynomial having coefficients obtained by converting coefficients of the first input polynomial. When the number of errors is larger than t/2, the arithmetic circuit outputs p/2 pieces of error position information based on the first evaluation values and third evaluation values obtained by converting the second evaluation values obtained by a third polynomial having (s+1)-th-order to t-th-order coefficients of the error locator polynomial.