Parallel Chien Search Circuit for Low-Latency FEC Decoding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-speed communication systems face challenges in efficiently decoding forward error correction (FEC) data due to the non-interleaved format of the final output frame, which hinders parallel processing and increases RAM requirements, leading to latency and reduced throughput.
Innovation Solution
A decoder circuit is designed to rearrange and buffer data, allowing multiple bits of a BCH data group to be accessed for parallel decoding, reducing RAM needs and enabling efficient parallel decoding operations without buffering the entire data packet, using a combination of M-bit BCH decoders and N-bit RS decoders configured for various data rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the final OTU frame stores the payload in a non-interleaved format, then the decoding can be performed sequentially, but multiple bits of a BCH group cannot be processed in parallel without first buffering and interleaving the OTU data, which increases RAM requirements and latency
Solution Approach 1:
The BCH data groups are segmented into multiple subsets, with each subset containing bits from different BCH groups that can be processed in parallel. This segmentation allows the decoder to process multiple bits simultaneously without requiring all bits of a single BCH group to be available, thereby reducing the buffering RAM requirements while maintaining high parallel processing throughput.
2Productivity
If buffering and interleaving the entire OTU data is performed to enable parallel processing, then parallel decoding can be achieved, but it increases latency and RAM requirements
Solution Approach 1:
The system performs preliminary organization of data into subsets of bits from different BCH groups that are pre-configured for parallel processing. This preliminary action allows the decoder to immediately begin parallel processing without waiting for complete buffering and interleaving of the entire OTU frame, thereby reducing latency while maintaining parallel processing capability.
3Reliability
If more powerful forward error correction codes are used to achieve greater correction capability, then BER correction capability is improved, but the complexity of decoding operations increases
Solution Approach 1:
The complex decoding task is segmented into multiple independent parallel decoding operations, each processing a subset of bits from different BCH groups. This segmentation allows the use of powerful FEC codes with greater correction capability while distributing the computational complexity across multiple simpler parallel units, thereby managing overall system complexity.
4Speed
If the decoder is designed for high-speed operation, then throughput is improved, but it becomes difficult to efficiently decode BCH encoded OTU data in parallel
Solution Approach 1:
The decoder employs dynamic data reorganization where incoming OTU data is dynamically sorted and distributed into multiple subsets based on which BCH group each bit belongs to. This dynamic organization enables high-speed parallel processing by ensuring that bits from different BCH groups are readily available in parallel processing units without requiring static pre-interleaving of the entire frame.
Data Source
AI summary
In one embodiment, a Chien search circuit includes a plurality of evaluation circuits, each configured to sequentially evaluate possible roots αi in a respective subset of possible roots of an error location polynomial (Λ(x)). Each evaluation circuit includes a respective sub-circuit for each of a plurality of coefficients λi (0≦i≦T) of the error location polynomial Λ(x) having T+1 coefficients. Each sub-circuit is configured to calculate one term of the error location polynomial for each possible root αi in the respective subset of possible roots. Each evaluation circuit is configured to evaluate the error location polynomial for each possible root in the respective subset of possible roots, as a sum of the terms calculated by the plurality of sub-circuits.