Parallel Chip Assembly Using Carrier Transfer and Laser Debonding
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Solution Overview
Problem
Current methods for bonding chips to a substrate are inefficient and uneconomical, especially when dealing with small chip sizes and large numbers, as they require manual handling and increased loading time.
Innovation Solution
A method involving a first carrier with attached chips using an adhesive layer, where a subset of chips is selectively attached to a conveyor carrier with a structured adhesive layer, and then released using laser debonding to be attached to a substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If individual chip handling and bonding is performed manually, then positioning accuracy is maintained, but productivity decreases and loading time increases
Solution Approach 1:
Multiple chips are arranged in arrays on carrier wafers and processed together in parallel. The method combines multiple individual chip bonding operations into a single parallel process, where arrays of chips are transferred and bonded simultaneously, dramatically increasing productivity while maintaining precision through automated alignment systems.
Solution Approach 2:
The process is divided into distinct stages: chip array preparation on carrier wafers, selective release of chip arrays, transfer to substrate, and bonding. This segmentation allows each stage to be optimized independently, with parallel processing occurring during the transfer and bonding phases, reducing overall loading time.
2Productivity
If parallel assembly is attempted, then productivity increases, but manufacturing complexity increases
Solution Approach 1:
Carrier wafers serve as intermediary substrates that hold arrays of chips in precise configurations. These carrier wafers act as temporary holding platforms that simplify the parallel handling of multiple chips, allowing automated transfer mechanisms to move entire chip arrays at once without requiring complex individual chip manipulation systems.
Solution Approach 2:
Chips are pre-arranged in precise arrays on carrier wafers before the bonding process. This preliminary organization eliminates the need for complex real-time positioning systems during bonding, as the chips are already in their final relative positions on the carrier, reducing assembly system complexity while maintaining high productivity.
3Manufacturing precision
If small chips are handled individually, then positioning precision is maintained, but ease of operation decreases
Solution Approach 1:
Multiple small chips are grouped into arrays on carrier wafers, transforming difficult-to-handle individual micro-chips into manageable array units. This merging approach maintains positioning precision through the structured array layout while dramatically improving ease of operation by allowing automated systems to handle entire arrays rather than individual microscopic components.
Solution Approach 2:
Carrier wafers act as intermediaries that provide a stable, macro-scale platform for holding and manipulating arrays of small chips. The carrier wafer's larger size and rigidity make it easy to handle with standard semiconductor equipment, while the chips themselves remain in precise positions on the carrier, combining ease of operation with manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables a high-precision parallel assembly of chips, improving efficiency and reducing handling difficulties, especially for small chips and large quantities.
Implementation Method 1
selectively releasing the subset of the plurality of chips from the first carrier by means of debonding (e.g., laser debonding) corresponding sections of the adhesive layer of the first carrier
Implementation Method 2
releasing the subset of the plurality of chips from the conveyor carrier by means of debonding (e.g., laser debonding) at least corresponding sections of the structured adhesive layer of the conveyor carrier
Implementation Method 3
providing a first carrier having attached thereto a plurality of chips by means of an adhesive layer of the first carrier
Data Source
AI summary
A method for manufacturing a device is provided. The method comprises providing a first carrier having attached thereto a plurality of chips by means of an adhesive layer of the first carrier, a first surface of the plurality of chips being attached to the first carrier. Further, the method comprises selectively attaching a second surface of a subset of the plurality of chips to a conveyor carrier by means of a structured adhesive layer of the conveyor layer. Further, the method comprises selectively releasing the subset of the plurality of chips from the first carrier by means of debonding corresponding sections of the adhesive layer of the first carrier. Further, the method comprises attaching the first surface of the subset of the plurality of chips to a substrate of the device.