Parallel Semiconductor Chip Pad Layout for Waveform Oscillation Suppression
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Solution Overview
Problem
Conventional semiconductor circuit devices face challenges in maintaining uniform resistance and reactance components between electrode pads of the same type when multiple semiconductor chips are connected in parallel, leading to oscillations in current and voltage waveforms during turn OFF, which can result in erroneous operation or device destruction.
Innovation Solution
The semiconductor circuit device employs a configuration where multiple semiconductor chips with different electrode pad layouts are mounted on a substrate, ensuring that the resistance and reactance components between electrode pads of the same type connected in parallel are uniform, achieved by optimizing the layout of electrode pads and the connection wiring.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multiple semiconductor chips are connected in parallel to increase current capacity, then the current handling capability is improved, but the resistance and reactance components between electrode pads become non-uniform, causing oscillations in current and voltage waveforms
Solution Approach 1:
The patent applies asymmetry by intentionally designing different electrode pad layouts for different semiconductor chips. Specifically, chips are arranged with varying pad positions and connection path lengths so that the total resistance and reactance from each chip's electrode pads to the external terminals are equalized. This asymmetric arrangement compensates for the non-uniformity that would otherwise occur in parallel connections, preventing waveform oscillations while maintaining high current capacity.
2Ease of manufacture
If electrode pads are arranged in a conventional uniform layout, then manufacturing is simplified, but resistance and reactance components between parallel-connected pads become non-uniform, leading to operational instability
Solution Approach 1:
The patent applies local quality by making each electrode pad layout unique according to its specific position and function within the parallel connection system. Instead of using a uniform layout for all chips, each chip's electrode pads are positioned with locally optimized characteristics - different distances, orientations, and connection path configurations - so that when connected in parallel, the overall resistance and reactance values are equalized. This localized customization ensures operational stability while remaining manufacturable.
Data Source
AI summary
A layout of electrode pads on a front surface of a first semiconductor chip is different from a layout of them on a second semiconductor chip. An overall layout of the semiconductor chips mounted on the insulated substrate and the layouts of the electrode pads on the front surfaces of the semiconductor chips including the first and second semiconductor chips are determined so that a value of a resistance component and/or a value of a reactance component between each two electrode pads that are the same type respectively on different semiconductor chips and are connected in parallel become the same. As a result, current waveform oscillation between semiconductor devices fabricated on the semiconductor chips, respectively, may be suppressed.