Parallel Semiconductor Chip Layout for Synchronous Switching
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Solution Overview
Problem
When controllable semiconductor elements are operated in parallel, uneven distribution of electric and thermal loads occurs due to differences in switching states and parasitic inductances, leading to reduced lifetime and potential for interbody-oscillations.
Innovation Solution
A semiconductor arrangement with a symmetrical design where the load paths of controllable semiconductor elements are connected in parallel through conductor tracks with identical parasitic inductances, capacities, and resistances, ensuring synchronous operation and balanced load distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If controllable semiconductor elements are electrically connected in parallel to achieve high rated current, then the current carrying capacity is improved, but uneven distribution of electric and thermal loads occurs due to differences in switching states and parasitic inductances
Solution Approach 1:
The patent applies asymmetry by intentionally introducing different inductance values in the electrical connections of parallel-connected semiconductor elements. Specifically, the connection with the higher switching voltage has lower inductance, while the connection with the lower switching voltage has higher inductance. This asymmetric design compensates for the natural differences in switching characteristics, ensuring that voltage spikes are balanced and load distribution becomes uniform across all parallel elements, thereby improving reliability while maintaining high power capability.
2Extent of automation
If common control voltage is fed to parallel-connected semiconductor elements using electrical lines, then synchronous operation is intended, but significantly different electric potentials at the first load electrodes cause different switching states
Solution Approach 1:
The patent addresses the equipotentiality issue by carefully designing the electrical connections to compensate for potential differences. By adjusting the inductance values in each connection path, the patent ensures that despite different switching voltages and parasitic inductances, the electric potentials at the load electrodes remain balanced during switching transitions. This maintains consistent switching states across all parallel elements, ensuring reliable synchronous operation.
3Power
If silicon-carbide-based semiconductor chips are connected in parallel due to their small footprint areas, then the current capacity is improved, but the problems of uneven load distribution and interbody-oscillations become more significant
Solution Approach 1:
The patent applies parameter changes by deliberately modifying the inductance parameters of the electrical connections. For silicon-carbide-based chips with small footprint areas that are connected in parallel to achieve higher current capacity, the patent introduces specific inductance values in each connection path. This parameter adjustment compensates for the inherent differences in switching characteristics of the parallel-connected chips, suppressing interbody-oscillations and ensuring uniform load distribution, thereby enabling reliable high-current operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The symmetrical design ensures identical voltage and current transfers across the semiconductor elements, maintaining synchronous switching behavior and improving short circuit strength, while also ensuring even temperature distribution and extended lifetime.
Implementation Method 1
conductor tracks with identical parasitic inductances, capacities, and resistances
Implementation Method 2
inevitable ohmic resistance and/or inductance of that line
Data Source
Figure 1~3
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Figure 5
AI summary
A semiconductor arrangement includes a circuit board comprising a metallization layer with a first conductor track and a second conductor track, and a multiplicity of individual semiconductor chips (1) each comprising a controllable semiconductor element (T), a first load electrode (11), a second load electrode (12) and a control electrode (13), the first load electrodes (11) of the individual semiconductor chips (1) electrically connected to one another, the second load electrodes (12) of the individual semiconductor chips (1) electrically connected to one another, and the control electrodes (13) of the individual semiconductor chips (1) electrically connected to one another. The first conductor track (M1) includes a base section (30) and a first, second and third section (31, 32, 33), the third section (33) arranged between the first and second sections (31, 32), and the second conductor track (M2) includes a first and a second section (41, 42). The first section (41) of the second conductor track (M2) is arranged between the first and the third section (31, 33) of the first conductor track (Ml), the second section (42) of the second conductor track (M2) is arranged between the second and the third section (32, 33) of the first conductor track (Ml), and the third section (33) of the first conductor track (M1) is arranged between the first and the second section (41, 42) of the second conductor track (M2). A first subset and a second subset of the multiplicity of semiconductor chips (1) are arranged on the first section (41) of the second conductor track (M2), and a third subset and a fourth subset of the multiplicity of semiconductor chips (1) are arranged on the second section (42) of the second conductor track (M2). The first load electrode (11) of each of the semiconductor chips (1) of the first and the second subset is, via at least one first electrical connection (51, 52), electrically connected to the first section (31) of the first conductor track (M1) and, via at least one second electrical connection (51, 52), to the third section (33) of the first conductor track (M1). Further, the first load electrode (11) of each of the semiconductor chips (1) of the third and the fourth subset is, via at least one third electrical connection (51, 52), electrically connected to the third section (33) of the first metallization (M1) and, via at least one fourth electrical connection (51, 52), to the second section (32) of the first conductor track (M1).