Parallel Chip Testing Circuit Reduces Verification Time
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Solution Overview
Problem
Conventional boundary scan methods for testing integrated circuit chips are time-consuming due to serial transmission and modification of test patterns, which is inefficient as the number of gate counts increases, and requires significant time to test and verify results.
Innovation Solution
A circuit and method that utilize a storage device, multiplexing modules, and selection devices to store and parallel transmit N-bit test patterns, generating M-bit results, allowing for parallel input and output, reducing the number of clock cycles required for testing and verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional boundary scan method with serial transmission is used, then testing can be performed without physical test probes, but time consumption is significant
Solution Approach 1:
The patent segments the test pattern data into multiple N-bit groups (first N-bit group, second N-bit group, third N-bit group, and fourth N-bit group) that can be stored separately in the storage device. This segmentation enables parallel loading and transmission of multiple test patterns simultaneously, transforming the serial transmission process into a parallel operation that significantly reduces testing time while maintaining the boundary scan capability.
Solution Approach 2:
The patent transitions from one-dimensional serial transmission to multi-dimensional parallel processing by utilizing multiple storage locations and multiple transmission paths. The storage device stores test patterns in different groups that can be accessed and transmitted in parallel, adding a temporal and spatial dimension to the testing process that eliminates the sequential bottleneck of conventional boundary scan methods.
2Measurement precision
If test patterns are modified for different modules, then accurate testing can be achieved, but extensive pattern modifications are required when modules change
Solution Approach 1:
The patent creates a universal testing system where the storage device can store multiple test pattern groups that are applicable to different module configurations. The multiplexing module and selection device work together to select and transmit the appropriate pre-stored test patterns without requiring modification, making the testing system adaptable to various module changes while maintaining testing accuracy. This universal approach eliminates the need for extensive pattern modifications when modules change.
Solution Approach 2:
The patent implements preliminary action by pre-storing multiple test pattern groups (first N-bit group, second N-bit group, third N-bit group, and fourth N-bit group) in the storage device before actual testing begins. These pre-prepared test patterns are designed to accommodate different module configurations, so when modules change, the system can simply select from the pre-stored patterns rather than modifying existing ones, significantly reducing the complexity of adapting to module changes.
3Device complexity
If serial transmission of test patterns is used, then simple circuit structure can be maintained, but productivity is reduced
Solution Approach 1:
The patent merges multiple test pattern transmission operations into a single parallel processing framework. By combining the storage of multiple N-bit groups in the storage device with the parallel transmission capability of the multiplexing module, the system achieves high-speed testing without significantly increasing circuit complexity. The selection device coordinates these parallel operations, effectively merging control functions to manage the enhanced productivity while maintaining relatively simple overall circuit structure.
Data Source
AI summary
Circuit and method for testing digital logic circuit modules of an integrated circuit chip. The circuit includes a storage device, a first multiplexing module and a selection device. The storage device stores first, second, third and fourth N-bit groups of a test pattern separately according to a loading signal and an address selection signal. The first multiplexing module is coupled to the storage device and a first digital logic circuit module, for parallel transmitting the first, second, third and fourth N-bit groups which will be received and executed by the first digital logic circuit module to parallel generate first, second and third M-bit groups. The selection device is coupled to the first digital logic circuit module for sequentially selecting one of the first, second and third M-bit groups to output a first test result according to the address selection signal.