Parallel Multi-Rate Circuit Simulation Using Hybrid Matrix Partitioning

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Solution Overview

Problem

Current circuit simulation methods face inefficiencies in parallel computation due to the bottleneck of LU decomposition, particularly in large, sparse circuit simulation matrices, which leads to slow convergence and high memory usage when applying Krylov-subspace methods at the top level.

Innovation Solution

A hybrid direct and iterative method is introduced, where the circuit Jacobian matrix is partitioned into loosely coupled blocks, reordered, and split into matrices M and N, with M being suitable for parallel processing and N serving as a coupling matrix, allowing for preconditioning and iterative solving to accelerate convergence.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If Krylov-subspace methods are applied at the top level of circuit simulation matrices, then convergence is achieved, but memory usage increases and computational overhead increases

Engineering Contradiction:
ImproveconvergenceVSAvoidmemory usage
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The circuit simulation matrix is segmented into subsystems using Schur complement decomposition. The top-level matrix is divided into block diagonal subsystems that can be solved independently with reduced memory requirements, while maintaining convergence through iterative coupling of the subsystems.

Inventive Principle:
Principle #1Segmentation

2Measurement precision

If LU decomposition is performed on large circuit simulation matrices, then accurate solutions are obtained, but fill-ins increase and computational overhead increases

Engineering Contradiction:
Improvesolution accuracyVSAvoidfill-ins
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The large circuit matrix is segmented into block diagonal subsystems via Schur complement decomposition. Each subsystem undergoes LU decomposition independently, significantly reducing fill-ins compared to decomposing the full dense top-level matrix, while maintaining solution accuracy through iterative refinement.

Inventive Principle:
Principle #1Segmentation

3Productivity

If parallel processing is applied to circuit simulation, then computational speed increases, but the bottleneck of LU decomposition limits scalability

Engineering Contradiction:
Improvecomputational speedVSAvoidscalability bottleneck
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The circuit simulation problem is segmented into independent block diagonal subsystems that can be processed in parallel. Each subsystem is solved independently using LU decomposition, eliminating the scalability bottleneck of traditional parallel LU decomposition on the full matrix while maintaining computational speed through efficient parallel execution of subsystems.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentEP1964010B1Parallel multi-rate circuit simulation
Publication Date: 2017.07.19 SYNOPSYS INC
  • EP1964010B1 patent drawingFigure 1
  • EP1964010B1 patent drawingFigure 2~3
  • EP1964010B1 patent drawingFigure 4

AI summary

A computer-implemented method for solving parallel equations in a circuit simulation is described. The method includes partitioning a circuit Jacobian matrix into loosely coupled partitions, reordering the voltage vector and the matrix according to the partitions, and splitting the Jacobian matrix into two matrices M and N, where M is a matrix suitable for parallel processing and N is a coupling matrix. M and N are then preconditioned to form M