Parallel Circuit Simulation Retiming Pipeline Regions
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Solution Overview
Problem
Existing parallel logic simulation techniques face inefficiencies, particularly with synchronization costs becoming high beyond a few processors, and uneven work distribution, leading to performance bottlenecks in multi-core computing systems.
Innovation Solution
The approach involves retiming a simulation model by partitioning the circuit design into pipeline regions, computing path lengths, and modifying them to achieve a target timing goal, which balances pipeline levels and reduces synchronization costs through selective evaluation and aggregation of primitives.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If parallel event driven simulation is used to improve simulation performance, then simulation throughput is improved, but synchronization cost increases significantly beyond four or eight processors
Solution Approach 1:
The circuit design is partitioned into multiple pipeline regions with combinational regions separated by register levels, creating independent simulation units that can be processed in parallel without requiring frequent synchronization between all processors
Solution Approach 2:
Path lengths of combinational regions are pre-computed and used to determine achievable timing goals and target retiming goals before simulation begins, allowing workload to be pre-balanced across pipeline levels to minimize synchronization requirements during actual simulation
2Productivity
If parallel event driven simulation is used to increase processing capacity, then more components can be simulated concurrently, but work distribution becomes uneven among processors
Solution Approach 1:
Different pipeline levels are assigned different numbers of processors based on their specific workload requirements, with more processors allocated to pipeline levels containing more combinational regions or longer path lengths, achieving localized optimization of resource allocation
Solution Approach 2:
The system dynamically adjusts the number of processors assigned to each pipeline level based on computed path lengths and timing goals, changing the parameter of processor allocation to match the computational demands of each pipeline region
3Ease of operation
If parallel oblivious simulation is used to simplify synchronization, then a single synchronization per level is sufficient, but redundant computation increases and efficiency decreases
Solution Approach 1:
Instead of evaluating all components in a pipeline level (excessive action), the system evaluates only those components within combinational regions that have been identified as having value changes or being relevant to the current simulation state, reducing redundant computation while maintaining synchronization simplicity
Data Source
AI summary
An approach for simulating a circuit design partitions the circuit design into pipeline regions that include one or more pipeline levels. A path length is computed for each combinational region within a pipeline region to compute an achievable timing goal for each pipeline region. A target retiming goal is determined for the set of pipeline regions based on the computed achievable timing goals of the pipeline regions. A pipeline region is identified from the set of pipeline regions that does not satisfy the target timing goal. A measure of slack is computed for each pipeline level in the identified pipeline region. Using the computed slack, path lengths of combinational regions in the pipeline levels of the identified pipeline region are iteratively retimed. The resulting circuit design is simulated using the retimed path lengths if the retimed critical path of the pipeline region satisfies the target timing goal.