Parallel Circuit Timing Analysis System
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Solution Overview
Problem
Current computer-aided design (CAD) and electronic design automation (EDA) tools for integrated circuits face significant computational challenges as circuit complexity increases, leading to inefficiencies in timing and signal integrity analysis due to bottlenecks in memory access and the need for repeated iterative computations, which parallel processing approaches fail to adequately address.
Innovation Solution
A distributed parallel processing system that uses multiple interconnected servers to concurrently execute timing analysis computations, with a control subsystem that aggregates results and assigns further computations, avoiding data structure locking and enabling efficient access to databases across servers, thereby reducing computation time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If parallel processing approaches are used to handle increased computational requirements, then processing capacity is improved, but bottlenecks such as memory access and data structure locking prevent adequate computational speedup
Solution Approach 1:
The patent segments the circuit analysis computation into independent modules that can be distributed across multiple processors. Each processor handles specific analysis tasks (e.g., timing analysis, signal integrity analysis) independently, eliminating the need for centralized data structure locking and allowing true parallel execution without memory access bottlenecks.
Solution Approach 2:
The patent introduces an intermediary mechanism (such as a message-passing interface or shared memory with relaxed consistency) that allows processors to exchange data without requiring simultaneous access to shared data structures. This intermediary layer decouples the processors from direct memory access conflicts, enabling scalable parallel processing.
2Measurement precision
If iterative techniques are used to determine signal integrity characteristics, then analysis accuracy is improved, but computation times grow faster than circuit size
Solution Approach 1:
The patent performs preliminary computations to establish initial signal integrity characteristics before the main iterative analysis. By pre-computing certain parameters and caching results, the system reduces the number of iterations needed in subsequent analyses, thereby maintaining accuracy while reducing overall computation time.
Solution Approach 2:
The patent implements continuous refinement of signal integrity results across multiple iterations, where each iteration builds upon previous results rather than starting from scratch. This continuous action approach maintains high accuracy while optimizing computation by reusing intermediate results and avoiding redundant calculations.
3Measurement precision
If analysis is begun anew after each circuit modification, then analysis accuracy is maintained, but computation costs increase significantly
Solution Approach 1:
The patent selectively discards and recovers computation results based on circuit modifications. When a circuit change occurs, the system identifies which analysis results remain valid and which need updating, recovering and reusing valid results while only re-computing affected portions. This maintains analysis accuracy while significantly reducing computation costs compared to complete re-analysis.
Solution Approach 2:
The patent implements a feedback mechanism that monitors circuit modifications and automatically triggers selective re-analysis only for affected circuit portions. The system uses feedback from the modification detection to determine which previously computed results can be retained and which must be updated, optimizing the balance between accuracy and computation cost.
4Measurement precision
If statistical timing analysis is used instead of best-case and worst-case limits, then timing prediction accuracy is improved, but computational requirements increase
Solution Approach 1:
The patent segments the statistical timing analysis into independent computational stages that can be executed in parallel. By dividing the statistical computations into discrete, manageable tasks (e.g., parameter extraction, distribution fitting, margin calculation), the system achieves high timing prediction accuracy while distributing computational load across multiple processors to manage complexity.
Data Source
AI summary
A system for circuit timing analysis includes a database for holding results of execution of portions of a timing analysis computation. Multiple computation modules are configured for concurrent execution of the portions of a timing analysis computation, for example, a static circuit timing analysis computation. A control subsystem is coupled to the database and to the computation modules, and is configured to receive results of the portions of the computation from the computation modules and to update the database using the received results. Based on the received results, the control module selects further portions of the computations for computation and assign each selected portion to one of the computation modules. The system makes use of parallel processing that is arranged in a way that avoids bottlenecks, such as at least some memory access bottlenecks resulting from data structure locking.