Parallel Interface Clock Deskew Using Training Signal Feedback
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Solution Overview
Problem
In semiconductor devices, skew between reference clock signals and data signals in parallel interface systems limits data transmission rates due to phase differences, reducing voltage and time margins, and existing deskew methods either require additional circuitry or increase manufacturing costs or reduce system performance.
Innovation Solution
A semiconductor device with a reference clock transmitting block, transceiver blocks, and a per-pin deskew block that adjusts the phase of the transmitting sampling clock signal based on phase skew information from training data or phase-controlled signals to reduce skew between the reference clock and data signals, combining per-pin deskew using clock and data recovery (CDR) and training data methods to minimize circuit area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If per-pin deskew using CDR is implemented, then skew reduction precision is improved, but circuit area and power consumption increase
Solution Approach 1:
The patent extracts only the essential deskew function from the full CDR circuit by implementing a simplified per-pin deskew mechanism that uses phase skew information from training data without requiring complete CDR circuitry, thereby reducing circuit area while maintaining skew reduction capability
Solution Approach 2:
The patent performs deskew calibration during a training phase before normal data transmission, using training data to pre-determine phase skew information and configure the per-pin deskew parameters in advance, which eliminates the need for complex real-time CDR circuits during operational phase
2Measurement precision
If per-pin deskew using CDR is implemented, then skew reduction precision is improved, but power consumption increases
Solution Approach 1:
The patent performs deskew calibration during a training phase before normal data transmission, using training data to pre-determine phase skew information and configure the per-pin deskew parameters in advance, which eliminates the need for complex real-time CDR circuits during operational phase
Solution Approach 2:
The patent extracts only the essential deskew function from the full CDR circuit by implementing a simplified per-pin deskew mechanism that uses phase skew information from training data without requiring complete CDR circuitry, thereby reducing power consumption while maintaining skew reduction capability
3Productivity
If data transmission rate is increased, then productivity is improved, but skew increases reducing voltage and time margins
Solution Approach 1:
The patent uses phase skew information obtained from training data as feedback to adjust and optimize the timing alignment between clock and data signals, enabling the system to maintain adequate voltage and time margins even at higher data transmission rates by compensating for skew effects
Solution Approach 2:
The patent performs skew measurement and compensation configuration during the training phase before high-rate data transmission begins, pre-optimizing the timing parameters to ensure adequate margins are maintained during subsequent high-speed operational phase
4Ease of operation
If conventional synchronizing process is used, then ease of operation is maintained, but skew occurs between data signal and reference clock signal
Solution Approach 1:
The patent introduces a training phase before normal operation where phase skew information is measured and stored, allowing the simple conventional synchronizing process to be enhanced with pre-calibrated skew compensation parameters without adding complexity to the main operational flow
Solution Approach 2:
The patent uses training data as an intermediary to transfer phase skew information from the transmission channel characteristics to the deskew control logic, enabling accurate phase alignment to be achieved through a separate calibration step rather than through complex real-time synchronization mechanisms
Data Source
AI summary
A method of communication to a semiconductor device includes: transmitting a sampling clock signal from a first semiconductor device to a second semiconductor device; transmitting a training signal from the first semiconductor device to the second semiconductor device while transmitting of the sampling clock signal, the training signal comprising plural test patterns sent sequentially to the second semiconductor device, phases of at least some of the test patterns being adjusted to be different from each other during transmitting of the training signal; receiving first information from the second semiconductor device over a first signal line, the first signal line separate from a data bus connected between the first semiconductor device and the second semiconductor device; and transmitting a data signal over the data bus while transmitting the sampling clock signal, the data signal sent at a timing with respect to the sampling clock signal responsive to the received first information.