Parallel Clock Impedance Adjustment for Low-Latency Memory Access
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Solution Overview
Problem
Memory devices face delays in switching on-die termination when sharing a common clock signal across multiple terminals, leading to increased operational latency.
Innovation Solution
Implementing impedance adjustment circuitry to provide a combined impedance equal to the clock impedance by connecting multiple terminals in parallel, using impedance detection and adjustment circuitry to match or exceed the impedance of the external clock signal, thereby eliminating the need for on-die termination switching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If on-die termination switching is used to share a common clock signal across multiple terminals, then device complexity is reduced, but operational latency increases due to switching delays
Solution Approach 1:
The patent applies preliminary action by pre-configuring multiple terminals with parallel impedance adjustment circuitry before the clock signal arrives. Each terminal's impedance is pre-adjusted to match the clock signal impedance, eliminating the need for switching during operation. This advance preparation removes the switching delay that causes operational latency while maintaining simplified device complexity.
Solution Approach 2:
The patent implements dynamics by making the impedance of each terminal adjustable and adaptive. The impedance adjustment circuitry dynamically modifies the terminal impedance to match the clock signal impedance, allowing the system to adapt to different operating conditions without physical switching. This dynamic adjustment eliminates switching delays while maintaining low device complexity.
2Speed
If multiple terminals are connected in parallel to share a common clock signal, then access speed to multiple memory sub-divisions improves, but impedance matching becomes more difficult
Solution Approach 1:
The patent applies parameter changes by modifying the impedance parameter of each terminal through adjustable impedance adjustment circuitry. Each terminal's impedance is tuned to compensate for the parallel connection effect, ensuring that the combined impedance matches the clock signal source impedance. This parameter adjustment enables fast simultaneous access to multiple memory sub-divisions while solving the impedance matching difficulty.
Solution Approach 2:
The patent implements feedback through impedance detection circuitry that monitors the actual impedance at each terminal and adjusts the impedance adjustment circuitry accordingly. This closed-loop feedback system automatically compensates for variations in parallel connection impedance, making impedance matching straightforward despite multiple terminals being connected in parallel for high-speed access.
Data Source
AI summary
Methods, systems, and apparatuses related to memory operation with common clock signals are provided. A memory device or system that includes one or more memory devices may be operable with a common clock signal without a delay from switching on-die termination on or off. For example, a memory device may comprise first impedance adjustment circuitry configured to provide a first impedance to a received clock signal having a clock impedance and second impedance adjustment circuitry configured to provide a second impedance to the received clock signal. The first impedance and the second impedance may be configured to provide a combined impedance about equal to the clock impedance when the first impedance adjustment circuitry and the second impedance adjustment circuitry are connected to the received clock signal in parallel.